Patents by Inventor Keiho Akiyama

Keiho Akiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6674485
    Abstract: The present invention provides an image compositing apparatus capable of producing a natural composite image, with a simple structure and a less occupying space. The present invention also provides a method for compositing an image by providing shadow-free conditions in a limited space for chroma-keying so that a subject image and a desired background image are naturally integrated as one image.
    Type: Grant
    Filed: August 26, 1999
    Date of Patent: January 6, 2004
    Assignee: Hitachi Software Engineering Co., Ltd.
    Inventors: Keiho Akiyama, Kou Otokozawa, Shigehiro Fukase, Naoto Baba, Yoshihiro Naitou, Tohru Baba
  • Publication number: 20030133044
    Abstract: The present invention provides an image compositing apparatus capable of producing a natural composite image, with a simple structure and a less occupying space. The present invention also provides a method for compositing an image by providing shadow-free conditions in a limited space for chroma-keying so that a subject image and a desired background image are naturally integrated as one image.
    Type: Application
    Filed: August 26, 1999
    Publication date: July 17, 2003
    Applicant: HITACHI SOFTWARE ENGINEERING CO LTD
    Inventors: KEIHO AKIYAMA, KOU OTOKOZAWA, SHIGEHIRO FUKASE, NAOTO BABA, YOSHIHIRO NAITOU, TOHRU BABA
  • Patent number: 4882690
    Abstract: A logic design automation system examines correspondence relationship among sublogics in intermediate gate-level logic (containing neither physical design information nor manually optimized logic design information) produced from updated functional-level logic and current gate-level logic (containing the above information) to identify corresponding sublogics and non-corresponding sublogics of the gate-level logics with reference to primary input/output signals and input/output gates. For the corresponding sublogics, the corresponding sublogics of the current gate-level logic are selected, and for the non-corresponding sublogics, the non-corresponding sublogics of the intermediate gate-level logic are selected. The selected sublogics are combined to synthesize updated gate-level logic which preserved therein the physical design information and the manually optimized logic design information for portions of the current gate-level logic which need not be modified.
    Type: Grant
    Filed: September 25, 1986
    Date of Patent: November 21, 1989
    Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering, Ltd., Hitachi Software Engineering Co., Ltd.
    Inventors: Takao Shinsha, Masato Morita, Yoshinori Sakataya, Yoji Tsuchiya, Mitsuhiro Hikosaka, Junji Koshishita, Keiho Akiyama, Takashige Kubo