Patents by Inventor Keiichi Fujimura

Keiichi Fujimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device and operation monitoring method for semiconductor device
    Patent number: 8742786
    Abstract: A semiconductor device includes a monitor including a first element coupled between a first power supply line and a second power supply line, and a load for increasing a load value between the first element and the first power supply line or the second power supply line, and a determination unit which determines an operating state of the first element based on an output of the monitor.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: June 3, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kazufumi Komura, Katsumi Furukawa, Keiichi Fujimura, Takayoshi Nakamura, Tohru Yasuda, Hirohisa Nishiyama, Nobuyoshi Nakaya, Kanta Yamamoto, Shigetaka Asano
  • Semiconductor integrated circuit device
    Patent number: 7663175
    Abstract: A semiconductor integrated circuit device provided with a plurality of power supply wire layers including a first potential power supply wire and a second potential power supply wire formed in different layers. At least one capacitor contact wire extends from one of the first and second potential power supply wires toward the other one of the first and second potential power supply wires so as to form a capacitor between each capacitor contact wire and its surrounding wires.
    Type: Grant
    Filed: May 30, 2006
    Date of Patent: February 16, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Kazufumi Komura, Takayoshi Nakamura, Keiichi Fujimura, Masahito Hirose, Keigo Nakashima, Masaki Nagato
  • SEMICONDUCTOR DEVICE AND OPERATION MONITORING METHOD FOR SEMICONDUCTOR DEVICE
    Publication number: 20090243627
    Abstract: A semiconductor device includes a monitor including a first element coupled between a first power supply line and a second power supply line, and a load for increasing a load value between the first element and the first power supply line or the second power supply line, and a determination unit which determines an operating state of the first element based on an output of the monitor.
    Type: Application
    Filed: March 24, 2009
    Publication date: October 1, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Kazufumi KOMURA, Katsumi Furukawa, Keiichi Fujimura, Takayoshi Nakamura, Tohru Yasuda, Hirohisa Nishiyama, Nobuyoshi Nakaya, Kanta Yamamoto, Shigetaka Asano
  • Power consumption reduction circuit for clock network
    Patent number: 7463076
    Abstract: A power consumption reduction circuit for reducing power consumed by a clock tree network including a transmission control circuit. The power consumption reduction circuit includes a transmission control circuit for controlling transmission of the clock signal to the buffer circuit group so as to selectively provide and interrupt the clock signal. A switch circuit disconnects the buffer circuit group from a power supply when the transmission control circuit interrupts the clock signal.
    Type: Grant
    Filed: September 8, 2005
    Date of Patent: December 9, 2008
    Assignee: Fujitsu Limited
    Inventors: Kazufumi Komura, Takayoshi Nakamura, Keiichi Fujimura, Masahito Hirose, Keigo Nakashima, Masaki Nagato
  • Semiconductor integrated circuit device
    Publication number: 20070195946
    Abstract: A semiconductor integrated circuit device provided with a plurality of power supply wire layers including a first potential power supply wire and a second potential power supply wire formed in different layers. At least one capacitor contact wire extends from one of the first and second potential power supply wires toward the other one of the first and second potential power supply wires so as to form a capacitor between each capacitor contact wire and its surrounding wires.
    Type: Application
    Filed: May 30, 2006
    Publication date: August 23, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Kazufumi Komura, Takayoshi Nakamura, Keiichi Fujimura, Masahito Hirose, Keigo Nakashima, Masaki Nagato
  • Power consumption reduction circuit for clock network
    Publication number: 20060220722
    Abstract: A power consumption reduction circuit for reducing power consumed by a clock tree network including a transmission control circuit. The power consumption reduction circuit includes a transmission control circuit for controlling transmission of the clock signal to the buffer circuit group so as to selectively provide and interrupt the clock signal. A switch circuit disconnects the buffer circuit group from a power supply when the transmission control circuit interrupts the clock signal.
    Type: Application
    Filed: September 8, 2005
    Publication date: October 5, 2006
    Inventors: Kazufumi Komura, Takayoshi Nakamura, Keiichi Fujimura, Masahito Hirose, Keigo Nakashima, Masaki Nagato