Patents by Inventor Keiichi Higeta
Keiichi Higeta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8050333Abstract: In a data transfer device which cancells an offset of a differential amplifier for amplifying a received signal and an offset caused by characteristics of a differential transmission line and selects optimum conditions such as pre-emphasis amount of an output pre-emphasis circuit, a first chip (transmission side LSI=transfer engine 210) and a second chip (reception side LSI=multiplexing engine 330) are connected to each other through differential transmission line 430 and a SerDes (serializer) 401 and a SerDes (deserializer) 402 are used to make signal transmission, so that optimum setting conditions of an offset amount of an offset cancellation circuit included in an input buffer amplifier and a pre-emphasis amount of pre-emphasis circuit included in an output buffer are decided in training using a training PRBS generator 560 and a training PRBS comparator 570.Type: GrantFiled: July 12, 2007Date of Patent: November 1, 2011Assignee: Hitachi, Ltd.Inventors: Takashi Muto, Yasuhiro Fujimura, Keiichi Higeta, Junji Baba, Takayuki Muranaka, Isao Kimura
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Patent number: 7620838Abstract: A circuit system is provided capable of improving the throughput thereof by eliminating the operational constraint that if the operating frequency of a content addressable memory is lower than the operating frequency of a system LSI, two system clocks should be provided, or the higher frequency should be synchronized with the slower system clock. A clock control circuit (103) for down-converting an internal clock (?1) of a LSI (101) is provided, and a control signal whose frequency is made lower is used to operate a content addressable memory circuit (102).Type: GrantFiled: October 18, 2005Date of Patent: November 17, 2009Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Takashi Koba, Naoyuki Anan, Mikiko Sakai, Seryung Park, Keiichi Higeta
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Patent number: 7596010Abstract: There is provided a control circuit (409) for fetching a result of a comparison of a part of bits of entry data with a corresponding bit of comparison data and prohibiting a comparison of residual bits in the entry data with the corresponding bit of the comparison data when the result of the comparison is mismatched, and the comparison of the residual bits in the entry data with the corresponding bit of the comparison data is prohibited. Consequently, the number of signal lines to be activated in one cycle of a comparing operation is decreased. Thus, a reduction in a consumed power can be achieved.Type: GrantFiled: February 12, 2008Date of Patent: September 29, 2009Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Masahiko Nishiyama, Keiichi Higeta, Takashi Koba
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Publication number: 20080144345Abstract: There is provided a control circuit (409) for fetching a result of a comparison of a part of bits of entry data with a corresponding bit of comparison data and prohibiting a comparison of residual bits in the entry data with the corresponding bit of the comparison data when the result of the comparison is mismatched, and the comparison of the residual bits in the entry data with the corresponding bit of the comparison data is prohibited. Consequently, the number of signal lines to be activated in one cycle of a comparing operation is decreased. Thus, a reduction in a consumed power can be achieved.Type: ApplicationFiled: February 12, 2008Publication date: June 19, 2008Inventors: Masahiko NISHIYAMA, Keiichi Higeta, Takashi Koba
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Patent number: 7349231Abstract: There is provided a control circuit (409) for fetching a result of a comparison of a part of bits of entry data with a corresponding bit of comparison data and prohibiting a comparison of residual bits in the entry data with the corresponding bit of the comparison data when the result of the comparison is mismatched, and the comparison of the residual bits in the entry data with the corresponding bit of the comparison data is prohibited. Consequently, the number of signal lines to be activated in one cycle of a comparing operation is decreased. Thus, a reduction in a consumed power can be achieved.Type: GrantFiled: February 28, 2007Date of Patent: March 25, 2008Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Masahiko Nishiyama, Keiichi Higeta, Takashi Koba
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Publication number: 20080013645Abstract: In a data transfer device which cancels an offset of a differential amplifier for amplifying a received signal and an offset caused by characteristics of a differential transmission line and selects optimum conditions such as pre-emphasis amount of an output pre-emphasis circuit, a first chip (transmission side LSI=transfer engine 210) and a second chip (reception side LSI=multiplexing engine 330) are connected to each other through differential transmission line 430 and a SerDes (serializer) 401 and a SerDes (deserializer) 402 are used to make signal transmission, so that optimum setting conditions of an offset amount of an offset cancellation circuit included in an input buffer amplifier and a pre-emphasis amount of pre-emphasis circuit included in an output buffer are decided in training using a training PRBS generator 560 and a training PRBS comparator 570.Type: ApplicationFiled: July 12, 2007Publication date: January 17, 2008Inventors: Takashi MUTO, Yasuhiro Fujimura, Keiichi Higeta, Junji Baba, Takayuki Muranaka, Isao Kimura
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Publication number: 20070183178Abstract: There is provided a control circuit (409) for fetching a result of a comparison of a part of bits of entry data with a corresponding bit of comparison data and prohibiting a comparison of residual bits in the entry data with the corresponding bit of the comparison data when the result of the comparison is mismatched, and the comparison of the residual bits in the entry data with the corresponding bit of the comparison data is prohibited. Consequently, the number of signal lines to be activated in one cycle of a comparing operation is decreased. Thus, a reduction in a consumed power can be achieved.Type: ApplicationFiled: February 28, 2007Publication date: August 9, 2007Inventors: Masahiko Nishiyama, Keiichi Higeta, Takashi Koba
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Patent number: 7203081Abstract: There is provided a control circuit (409) for fetching a result of a comparison of a part of bits of entry data with a corresponding bit of comparison data and prohibiting a comparison of residual bits in the entry data with the corresponding bit of the comparison data when the result of the comparison is mismatched, and the comparison of the residual bits in the entry data with the corresponding bit of the comparison data is prohibited. Consequently, the number of signal lines to be activated in one cycle of a comparing operation is decreased. Thus, a reduction in a consumed power can be achieved.Type: GrantFiled: December 27, 2004Date of Patent: April 10, 2007Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Masahiko Nishiyama, Keiichi Higeta, Takashi Koba
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Publication number: 20060085661Abstract: A circuit system is provided capable of improving the throughput thereof by eliminating the operational constraint that if the operating frequency of a content addressable memory is lower than the operating frequency of a system LSI, two system clocks should be provided, or the higher frequency should be synchronized with the slower system clock. A clock control circuit (103) for down-converting an internal clock (?1) of a LSI (101) is provided, and a control signal whose frequency is made lower is used to operate a content addressable memory circuit (102).Type: ApplicationFiled: October 18, 2005Publication date: April 20, 2006Inventors: Takashi Koba, Naoyuki Anan, Mikiko Sakai, Seryung Park, Keiichi Higeta
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Patent number: 7012848Abstract: The present invention provides a novel semiconductor integrated circuit device equipped with memory circuits, high-speed memories and large memory capacity memory circuits, which enables speeding up and facilitation of timing settings.Type: GrantFiled: August 13, 2004Date of Patent: March 14, 2006Assignee: Renesas Technology CorporationInventors: Satoshi Iwahashi, Shigeru Nakahara, Takeshi Suzuki, Keiichi Higeta
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Patent number: 7009862Abstract: Data lines (D0, D1) are shared by a first storage portion (MA) and a second storage portion (MB), and furthermore, a first transistor (MC0) coupled to a first comparison data portion (CD0) and a second transistor (MCA) coupled to the storage node of a first storage portion are connected in series to form a first comparing circuit (11), and a third transistor (MC1) coupled to a second comparison data line (CD1) and a fourth transistor (MCB) coupled to the storage node of the second storage portion are connected in series to form a second comparing circuit (12). Consequently, it is possible to enhance a symmetry in the layout of a diffusion layer and a wiring layer and to achieve the easiness of a layout in which a memory cell is line symmetrical with respect to a center line passing through a center thereof. Thus, a manufacturing process condition can easily be optimized and a variation in a manufacturing process can be reduced so that the microfabrication of the memory cell can be achieved.Type: GrantFiled: December 15, 2004Date of Patent: March 7, 2006Assignee: Hitachi, Ltd.Inventors: Keiichi Higeta, Satoshi Iwahashi, Yoichiro Aihara, Shigeru Nakahara
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Patent number: 7009246Abstract: To reduce the width of isolation between the first and second p channel MIS•FETs driven by different voltages, a first p channel MIS•FET driven by a first supply voltage and a second p channel MIS•FET driven by a second supply voltage higher than the first supply voltage are arranged in the same n well of the same semiconductor substrate, and the second supply voltage is supplied as a common well bias voltage to the n well.Type: GrantFiled: February 6, 2004Date of Patent: March 7, 2006Assignee: Hitachi, Ltd.Inventors: Takahiro Kawata, Shigeru Nakahara, Keiichi Higeta
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Patent number: 6998878Abstract: To speed up the operation of a decoder circuit, reduce the power consumption of the decoder circuit and increase the cycle, each circuit such as a buffer, a predecoder and a main decoder in the decoder circuit includes a semiconductor logic circuit in which the number of columns of transistors for pulling down at an output node is small, even if the number of inputs is many and the true and a complementary output signal having approximately the same delay time are acquired and the output pulse length of each circuit in the decoder circuit is reduced. With this arrangement, the operation of the decoder circuit can be sped up, the power consumption can be reduced, the cycles can be increased and, in a semiconductor memory, for example, access time and power consumption can be reduced and the cycles can be increased.Type: GrantFiled: January 12, 2004Date of Patent: February 14, 2006Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Kazuo Kanetani, Hiroaki Nambu, Kaname Yamasaki, Takeshi Kusunoki, Keiichi Higeta, Kunihiko Yamaguchi, Fumihiko Arakawa
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Publication number: 20060031655Abstract: The present invention is directed to facilitate change in the specifications of an interface of a memory IP and to improve reusability of the memory IP. A memory module to be mounted on a system LSI or the like is constructed by a basic array and an interface. The basic array is constructed by direct peripheral circuits and a storage circuit. Library data of the basic array is stored in a storage medium such as a CD-R or a magnetic tape and distributed to the user. The library data includes layout pattern data, a logic simulation model defining the operation of the basic array, LSI pattern information such as a layout, device information such as characteristics of a MOS device and layout rules, interface information such as various signal timings, and device specification data such as terminal information.Type: ApplicationFiled: October 5, 2005Publication date: February 9, 2006Inventors: Kei Kato, Masanao Yamaoka, Keiichi Higeta, Kazumasa Yanagisawa, Shigeru Shimada, Kodo Yamauchi, Yoshihiro Shinozaki, Yasuo Taguchi
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Patent number: 6920071Abstract: A semiconductor integrated circuit device endowed with memory circuits achieving high operation margin and low energy consumption with high speed and high integration. Composing a memory cell with a MOSFET having a first threshold voltage corresponding to a first voltage and supplying a selection signal corresponding to said first voltage to a word line by a word driver driven at said first voltage. Corresponding to a second voltage smaller than said first voltage, forming a selection signal sending to said word driver by a decoder comprising MOSFET with a second threshold voltage smaller than said first voltage, operating at said first voltage, and installing a first level shifting circuit including inverter circuits that form a selection signal corresponding to said first voltage by receiving a selection signal corresponding to said second voltage. Thereby, high operation margin and low energy consumption with high speed and high integration can be achieved.Type: GrantFiled: May 14, 2004Date of Patent: July 19, 2005Assignee: Hitachi, Ltd.Inventors: Takahiro Kawata, Shigeru Nakahara, Keiichi Higeta
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Publication number: 20050152167Abstract: There is provided a control circuit (409) for fetching a result of a comparison of a part of bits of entry data with a corresponding bit of comparison data and prohibiting a comparison of residual bits in the entry data with the corresponding bit of the comparison data when the result of the comparison is mismatched, and the comparison of the residual bits in the entry data with the corresponding bit of the comparison data is prohibited. Consequently, the number of signal lines to be activated in one cycle of a comparing operation is decreased. Thus, a reduction in a consumed power can be achieved.Type: ApplicationFiled: December 27, 2004Publication date: July 14, 2005Inventors: Masahiko Nishiyama, Keiichi Higeta, Takashi Koba
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Publication number: 20050146947Abstract: Data lines (D0, D1) are shared by a first storage portion (MA) and a second storage portion (MB), and furthermore, a first transistor (MC0) coupled to a first comparison data portion (CD0) and a second transistor (MCA) coupled to the storage node of a first storage portion are connected in series to form a first comparing circuit (11), and a third transistor (MC1) coupled to a second comparison data line (CD1) and a fourth transistor (MCB) coupled to the storage node of the second storage portion are connected in series to form a second comparing circuit (12). Consequently, it is possible to enhance a symmetry in the layout of a diffusion layer and a wiring layer and to achieve the easiness of a layout in which a memory cell is line symmetrical with respect to a center line passing through a center thereof. Thus, a manufacturing process condition can easily be optimized and a variation in a manufacturing process can be reduced so that the microfabrication of the memory cell can be achieved.Type: ApplicationFiled: December 15, 2004Publication date: July 7, 2005Inventors: Keiichi Higeta, Satoshi Iwahashi, Yoichiro Aihara, Shigeru Nakahara
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Patent number: 6876573Abstract: A semiconductor memory device having a memory array comprising CMOS flip-flop circuit type memory cells, which is capable of improving a noise margin, making a read rate fast and reducing power consumption. In the semiconductor memory device, an operating voltage of the memory cell is set higher than an operating voltage of each of peripheral circuits. Threshold voltages of MOS transistors that constitute the memory cell, are set higher than those of MOS transistors constituting the peripheral circuit. A gate insulting film for the MOS transistors that constitute the memory cell, is formed so as to be regarded as thicker than a gate insulting film for the MOS transistors constituting the peripheral circuit when converted to an insulating film of the same material. Further, a word-line selection level and a bit-line precharge level are set identical to the level of the operating voltage of the peripheral circuit.Type: GrantFiled: August 13, 2004Date of Patent: April 5, 2005Assignee: Renesas Technology CorporationInventors: Keiichi Higeta, Shigeru Nakahara, Hiroaki Nambu
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Patent number: 6856574Abstract: A semiconductor memory device comprises a memory-cell array for storing data, a peripheral circuit for carrying out an operation to read out or write data from or into the memory-cell array, read clock generation circuits (111, 113 and 115) each used for generating a read clock signal to be supplied to the peripheral circuit in the operation to read out data from the memory-cell array, write clock generation circuits (112, 114 and 116) each used for generating a write clock signal to be supplied to the peripheral circuit in the operation to write data into the memory-cell array. Since the pulse widths of the clock signals in read and writes are adjusted individually, margin insufficiencies of the pulse widths can be evaluated and results of the evaluation can be fed back to a design phase for, among other purposes, correction of a layout.Type: GrantFiled: November 25, 2003Date of Patent: February 15, 2005Assignee: Hitachi, Ltd.Inventors: Satoshi Iwahashi, Keiichi Higeta
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Publication number: 20050013159Abstract: The present invention provides a novel semiconductor integrated circuit device equipped with memory circuits, high-speed memories and large memory capacity memory circuits, which enables speeding up and facilitation of timing settings.Type: ApplicationFiled: August 13, 2004Publication date: January 20, 2005Inventors: Satoshi Iwahashi, Shigeru Nakahara, Takeshi Suzuki, Keiichi Higeta