Abstract: A p-type source region 2 and a p-type drain region 3 are formed on the surface of an n-type semiconductor layer 1. In the position located above a channel region interposed between the p-type source region 2 and the p-type drain region 3 and overlapping the p-type drain region 3, a charge accumulation electrode 5 is formed with a tunnel oxide film 4 interposed therebetween. In the position located above the channel region interposed between the p-type source region 2 and the p-type drain region 3 and overlapping the p-type source region 2, a select electrode 7 is formed with an insulating film 6 interposed therebetween. Above the charge accumulation electrode 5, a control electrode 9 is formed with the insulating film 8 interposed therebetween.

Abstract: A p-type source region 2 and a p-type drain region 3 are formed on the surface of an n-type semiconductor layer 1. In the position located above a channel region interposed between the p-type source region 2 and the p-type drain region 3 and overlapping the p-type drain region 3, a charge accumulation electrode 5 is formed with a tunnel oxide film 4 interposed therebetween. In the position located above the channel region interposed between the p-type source region 2 and the p-type drain region 3 and overlapping the p-type source region 2, a select electrode 7 is formed with an insulating film 6 interposed therebetween. Above the charge accumulation electrode 5, a control electrode 9 is formed with the insulating film 8 interposed therebetween.