Abstract: A semiconductor device includes first and second buffers respectively outputting reception data and clock signals; a latch circuit latching the reception data signal in response to the reception clock signal; a delay circuitry delaying the reception clock signal by a set delay time; and a delay control circuitry which searches a first delay time while increasing the set delay time from an initial value; searches a second delay time while increasing the set delay time from the first delay time; searches a third delay time while decreasing the set delay time from the second delay time; and determines an optimum delay time from the first and third delay times. The first and third delay times are determined so that the reception data is stabilized to a first value and the second delay time is determined so that the reception data is stabilized to a second value.

Abstract: A semiconductor device includes first to sixth external connection terminals, a first receiver connected to the first and second external connection terminals, a second receiver connected to the third and fourth external connection terminals, a third receiver connected to the fifth and sixth external connection terminals, a C-PHY block, a D-PHY block and a main processing section. The C-PHY block is configured to generate first reception data by performing signal processing on signals received from the first, second and third receivers in accordance with the MIPI C-PHY specification. The D-PHY block is configured to generate second reception data by performing signal processing on signals received from the first, second and third receivers in accordance with the MIPI D-PHY specification. The main processing section is configured to selectively receive the first and second reception data and perform desired processing on the received data.

Abstract: A semiconductor device includes first and second buffers respectively outputting reception data and clock signals; a latch circuit latching the reception data signal in response to the reception clock signal; a delay circuitry delaying the reception clock signal by a set delay time; and a delay control circuitry which searches a first delay time while increasing the set delay time from an initial value; searches a second delay time while increasing the set delay time from the first delay time; searches a third delay time while decreasing the set delay time from the second delay time; and determines an optimum delay time from the first and third delay times. The first and third delay times are determined so that the reception data is stabilized to a first value and the second delay time is determined so that the reception data is stabilized to a second value.

Abstract: A semiconductor device includes first to sixth external connection terminals, a first receiver connected to the first and second external connection terminals, a second receiver connected to the third and fourth external connection terminals, a third receiver connected to the fifth and sixth external connection terminals, a C-PHY block, a D-PHY block and a main processing section. The C-PHY block is configured to generate first reception data by performing signal processing on signals received from the first, second and third receivers in accordance with the MIPI C-PHY specification. The D-PHY block is configured to generate second reception data by performing signal processing on signals received from the first, second and third receivers in accordance with the MIPI D-PHY specification. The main processing section is configured to selectively receive the first and second reception data and perform desired processing on the received data.

Abstract: A receiver is composed of a receiver-side amplifier which receives a clock signal, a receiver-side amplifier which receives a data signal, a variable delay circuit which generates a delay-adjusted clock signal and a delay-adjusted data signal by delaying the clock signal and the data signal, a latch circuit section which latches the delay-adjusted data signal in synchronous with the delay-adjusted clock signal, and a skew detecting circuit which generates skew detection data that by latching a specific data sequence transmitted as the data signal in synchronous with a first clock signal to Nth clock signal (N is an integer equal to or more than 2) with different delay times from the clock signal. The delay time in the variable delay circuit is controlled according to the skew detection data.

Abstract: A receiver is composed of a receiver-side amplifier which receives a clock signal, a receiver-side amplifier which receives a data signal, a variable delay circuit which generates a delay-adjusted clock signal and a delay-adjusted data signal by delaying the clock signal and the data signal, a latch circuit section which latches the delay-adjusted data signal in synchronous with the delay-adjusted clock signal, and a skew detecting circuit which generates skew detection data that by latching a specific data sequence transmitted as the data signal in synchronous with a first clock signal to Nth clock signal (N is an integer equal to or more than 2) with different delay times from the clock signal. The delay time in the variable delay circuit is controlled according to the skew detection data.

Abstract: A liquid crystal drive controller comprises first lines drawn from the input terminals of a strobing comparator, first external terminals capable of connecting the first lines to strobing transmission lines, second lines drawn from a strobing offset current source, and second external terminals capable of connecting the second lines to the strobing transmission lines. The first lines and the first external terminals, and the second lines and the second external terminals are electrically insulated from each other on the liquid crystal drive controller. First wires and second wires are connected to strobing terminals so that the first wires are not included in the strobing offset current path, thereby eliminating a shortage of margin.

Abstract: A time constant circuit capable of switching the characteristic, which is realized by a combination of an equivalent resistor made up of a switched capacitor and an ordinary capacitor, comprises a capacitor of the switched capacitor or the time constant circuit connected in parallel to a series circuit including a switching device and an additional capacitor. The characteristic is switched by turning on and off the additional capacitor by the switching device. The direct connection of a plurality of equivalent resistors with a plurality of switched capacitors and ordinary capacitors makes up an equalizer. The capacitor making up a switched capacitor is connected with a switching device and an additional capacitor so that the frequency characteristic of the equalizer is switchable by turning on and off the switching device. Each of the capacitors making up the switched capacitors, the capacitors making up the time constant circuits and the additional capacitors has an end thereof grounded.

Abstract: A signal voltage dividing circuit in which two switched capacitors each including an input terminal, an output terminal and a capacitor connected selectively to the input terminal or the output terminal are connected in series and driven in opposite phase with each other. A holding capacitor is connected between the junction of the two switched capacitors and a reference potential. An input signal is supplied across the two switched capacitors to produce a divided output signal from the junction of the two switched capacitors.