Abstract: A thermosetting resin composition containing a maleimide compound (a) having at least one N-substituted maleimide group, and a compound (b) represented by the following general formula (1) exhibiting no reactivity with the maleimide group of the component (a) (Xb1 represents a single bond or a substituted or unsubstituted aliphatic hydrocarbon group having 1 to 5 carbon atoms; Rb1 and Rb2 each independently represent a substituted or unsubstituted aliphatic hydrocarbon group having 1 to 10 carbon atoms, a substituted or unsubstituted aromatic hydrocarbon group having 6 to 18 ring carbon atoms, a substituted or unsubstituted heterocyclic aromatic hydrocarbon group having 5 to 20 ring atoms, an oxygen atom-containing group, or a group containing a combination of these groups; and m and n each independently represent an integer of 0 to 5).

Abstract: To improve the convenience of handling. It includes a communication unit capable of wirelessly communicating with an imaging apparatus; a display control unit that displays information regarding the imaging apparatus on the basis of communication with the imaging apparatus; and an attachable/detachable portion that is engageable with a locking portion of an accessory and attachable/detachable to/from the locking portion of the accessory. Accordingly, since it can be wirelessly connected to the imaging apparatus and control can be performed on the imaging apparatus in a state where the control apparatus is locked to the accessory, it is possible to improve the convenience of handling.

Abstract: A spread spectrum clock generator includes a phase comparator that compares a reference clock with a feedback clock, a low-pass filter that passes a predetermined low-frequency component, a phase lock loop that includes a voltage-controlled oscillator generating an output clock whose frequency corresponds to the filtered signal, a triangular wave controller that generates a triangular wave signal for frequency-modulating the spread spectrum clock based on the output clock, a delay controller that generates the feedback clock by controlling delay of the output clock based on the triangular wave signal, a first counter that counts the output clock and output a first count value, a second counter that counts the reference clock and output a second count value, and a phase error correction circuit that compares the first count value with the second count value and corrects phase error of the output clock.

Abstract: A memory control device includes a plurality of delay circuits to set a delay value for each terminal of a memory, each of the plurality of delay circuits being connected to a terminal of the memory. Further, the memory control device includes a first register to store a first DLL value output by a delay locked loop circuit, a plurality of second registers to store a first setting value to set the delay value for the each terminal of the memory, each of the plurality of second registers being connected to a delay circuit of the plurality of delay circuits, and a delay controller to calculate a second setting value based on the first DLL value, a second DLL value output by the delay locked loop circuit after the first DLL value, and the first setting value, and to update the first setting value to the second setting value.

Abstract: A spread spectrum clock generator includes a phase comparator that compares a reference clock with a feedback clock, a low-pass filter that passes a predetermined low-frequency component, a phase lock loop that includes a voltage-controlled oscillator generating an output clock whose frequency corresponds to the filtered signal, a triangular wave controller that generates a triangular wave signal for frequency-modulating the spread spectrum clock based on the output clock, a delay controller that generates the feedback clock by controlling delay of the output clock based on the triangular wave signal, a first counter that counts the output clock and output a first count value, a second counter that counts the reference clock and output a second count value, and a phase error correction circuit that compares the first count value with the second count value and corrects phase error of the output clock.

Abstract: A memory control device includes a plurality of delay circuits to set a delay value for each terminal of a memory, each of the plurality of delay circuits being connected to a terminal of the memory. Further, the memory control device includes a first register to store a first DLL value output by a delay locked loop circuit, a plurality of second registers to store a first setting value to set the delay value for the each terminal of the memory, each of the plurality of second registers being connected to a delay circuit of the plurality of delay circuits, and a delay controller to calculate a second setting value based on the first DLL value, a second DLL value output by the delay locked loop circuit after the first DLL value, and the first setting value, and to update the first setting value to the second setting value.

Abstract: An image processing apparatus includes a scanning unit which scans a reference image data generated by dividing an input image data having distortion into plural areas, a storage which stores the scanned image data, a processing range determining unit which determines a range for the image data to be processed among the stored image data, and a correcting unit which performs a distortion correction on the image data within the determined range. The processing range determining unit determines the range to be larger than the reference image data.

Abstract: A memory control device includes a plurality of delay circuits to set a delay value for each terminal of a memory, each of the plurality of delay circuits being connected to a terminal of the memory. Further, the memory control device includes a first register to store a first DLL value output by a delay locked loop circuit, a plurality of second registers to store a first setting value to set the delay value for the each terminal of the memory, each of the plurality of second registers being connected to a delay circuit of the plurality of delay circuits, and a delay controller to calculate a second setting value based on the first DLL value, a second DLL value output by the delay locked loop circuit after the first DLL value, and the first setting value, and to update the first setting value to the second setting value.

Abstract: A disclosed synchronous memory control apparatus for enabling reception of data read from a memory circuit in synchronism with a strobe signal from the memory circuit includes a mask circuit masking the strobe signal using a mask signal; a timing measuring circuit delaying the strobe signal in plural units of delay and latching data of each of the delayed strobe signals; and a mask generating circuit generating the mask signal. The timing measuring circuit latches the data of each of the delayed strobe signals at the first rise edge of the corresponding masked strobe signal. The mask generating circuit includes a delay circuit having plural units of delay. A start timing of the mask signal is adjusted in synchronism with an internal clock, and a signal having a delay amount corresponding to a selected unit of delay by the delay circuit is outputted as the mask signal.

Abstract: An image pickup apparatus includes a housing, a lens incorporated in the front of the housing and configured to constitute an imaging optical system, an image pickup device provided in the housing and configured to capture a subject image guided by the imaging optical system, a printed wiring board provided in the housing and having the image pickup device mounted thereon, a barrel provided integrally with the front of the housing, an annular lens cover configured to push a face of the lens facing forward in a rearward direction, and detachably mounted on the front of the barrel, and a support wall projecting rearward outside a rear end of the barrel in the radial direction and inside the housing, and bonded to the printed wiring board with adhesive.

Abstract: A disclosed synchronous memory control apparatus for enabling reception of data read from a memory circuit in synchronism with a strobe signal from the memory circuit includes a mask circuit masking the strobe signal using a mask signal; a timing measuring circuit delaying the strobe signal in plural units of delay and latching data of each of the delayed strobe signals; and a mask generating circuit generating the mask signal. The timing measuring circuit latches the data of each of the delayed strobe signals at the first rise edge of the corresponding masked strobe signal. The mask generating circuit includes a delay circuit having plural units of delay. A start timing of the mask signal is adjusted in synchronism with an internal clock, and a signal having a delay amount corresponding to a selected unit of delay by the delay circuit is outputted as the mask signal.

Abstract: An information processor that is connected to at least one other information processor via a network, includes a detecting unit that detects an optional device to be used for information processing, as a target optional device, installed on the other information processor, an issuing unit that issues an access request to use the target optional device to the other information processor, a receiving unit that receives an access permission for access to the target optional device from the other information processor, and a processing unit that performs the information processing with the target optional device.

Abstract: First to fourth lenses are aligned in an optical axis direction by a lens-barrel of a camera, an O-ring is disposed between the first lens and the lens-barrel, an O-ring is disposed between the fourth lens and the lens-barrel, a space is formed between the first and second lenses, a space is formed between the second and fourth lenses, a space is formed between the third and fourth lenses, and flow of air between the spaces is precluded. The camera thus configured is free of dewing on the lens or a protective plate exposed to the exterior, even when the inside temperature is raised due to heat generation in a CCD or a mounting substrate on which the CCD is mounted.

Abstract: A high-speed serial switch fabric is configured to perform a mapping of a traffic class that is capable of differentiating traffics onto a virtual channel. The high-speed serial switch fabric connects a plurality of devices. A traffic-class setting unit sets, when a conflict occurs between devices connected to the high-speed serial switch fabric, the traffic class for each of traffics in the devices having the conflict. A channel setting unit assigns each of set traffic classes to different virtual channels, and gives a priority of data communication to each of the set traffic classes.

Abstract: A memory control device is disclosed that comprises a clock generator that generates a reference clock, a DLL circuit that receives the reference clock from the clock generator and outputs an output value indicative of a clock cycle of the reference clock, a delay setting circuit that receives the output value from the DLL circuit and outputs a delay setting value based on the output value according to at least one parameter, and plural delay elements that receive the delay setting value and introduce a delay responsive to the delay setting value. One or more of the delay elements receive input signals from corresponding one or more flip-flops driven by drive clocks generated by the clock generator, and send output signals to corresponding one or more output buffers that are to be connected to a memory.

Abstract: A memory control device is disclosed that comprises a clock generator that generates a reference clock, a DLL circuit that receives the reference clock from the clock generator and outputs an output value indicative of a clock cycle of the reference clock, a delay setting circuit that receives the output value from the DLL circuit and outputs a delay setting value based on the output value according to at least one parameter, and plural delay elements that receive the delay setting value and introduce a delay responsive to the delay setting value. One or more of the delay elements receive input signals from corresponding one or more flip-flops driven by drive clocks generated by the clock generator, and send output signals to corresponding one or more output buffers that are to be connected to a memory.

Abstract: An image pickup apparatus includes a housing, a lens incorporated in the front of the housing and configured to constitute an imaging optical system, an image pickup device provided in the housing and configured to capture a subject image guided by the imaging optical system, a printed wiring board provided in the housing and having the image pickup device mounted thereon, a barrel provided integrally with the front of the housing, an annular lens cover configured to push a face of the lens facing forward in a rearward direction, and detachably mounted on the front of the barrel, and a support wall projecting rearward outside a rear end of the barrel in the radial direction and inside the housing, and bonded to the printed wiring board with adhesive.

Abstract: A high-speed serial switch fabric is configured to perform a mapping of a traffic class that is capable of differentiating traffics onto a virtual channel. The high-speed serial switch fabric connects a plurality of devices. A traffic-class setting unit sets, when a conflict occurs between devices connected to the high-speed serial switch fabric, the traffic class for each of traffics in the devices having the conflict. A channel setting unit assigns each of set traffic classes to different virtual channels, and gives a priority of data communication to each of the set traffic classes.

Abstract: An information processor that is connected to at least one other information processor via a network, includes a detecting unit that detects an optional device to be used for information processing, as a target optional device, installed on the other information processor, an issuing unit that issues an access request to use the target optional device to the other information processor, a receiving unit that receives an access permission for access to the target optional device from the other information processor, and a processing unit that performs the information processing with the target optional device.

Abstract: A delay control apparatus includes first and second delay elements each configured to receive and delay a strobe signal and clock by a prescribed delay value. A prescribed number of flip-flops is provided to input data upon receiving the strobe signal output from the second delay element. The second delay element delays and outputs the strobe signal by the prescribed delay value to the flip-flops when the selection device selects the strobe signal. A phase comparator compares clocks output from the first and second delay elements. A delay control device changes the prescribed delay value of the second delay element in accordance with the comparison result of the phase comparator when the selection device selects the clock.