Abstract: A product development management system, comprising: a product database storage unit configured to be registered information relating to a product for which an order is registered; a product knowledge database storage unit to be registered information relating to a product having a past record of manufactures; and a central processing control unit configured to have a decision module configured to forecast a product after manufacturing by referring to said product database storage unit and said product knowledge database unit and decide whether said product satisfies predetermined conditions.

Abstract: A group work control system 10 is implemented with a network including respective terminals 1a to 1c connected to each other by a communication line 4 and serves to control development work and the like having a plurality of work steps through the network. The group work control system 10 comprises a server 2 serving to provide a schedule file in which is written the schedule of the work steps and a group work cooperation program running on the terminal 1a to 1c for displaying the work items to be conducted in the respective work steps.

Abstract: A conductor layer is formed on an insulating film which is formed on a semiconductor substrate and which consists of a thick portion and a thin portion with a step therebetween. A film made of material having an etch rate substantially equal to that of the material of the conductor layer is formed on the layer. The film, which has a substantially flat upper surface, and the conductor layer form a laminated structure. Those portions of the laminated structure which are on the thin portion of the insulating film and said step have substantially the same thickness. A mask layer of a predetermined pattern is formed on the laminated structure. Using the mask layer, the laminated structure is selectively etched, the selected portions of the conductor layer and film being etched at the same etching rate. Thereafter, the mask layer and the remaining film are removed.

Abstract: Disclosed is a memory device having a plurality of memory cells arranged in a matrix form; address buses connected to the memory cells and forming respective rows of the matrix; and data buses connected to the memory cells and forming respective columns of the matrix.The address buses or the data buses are formed by paired bus lines, and bridge lines are formed between one and the other of the paired bus lines.