Abstract: A single-chip microcomputer has external terminals outputting a system clock signal, an address signal, and a data signals. External equipment such as an external memory is operated by address and signal which are output when the system clock signal changes. In the single-chip microcomputer of this invention, the operation of an address signal output circuit and that of a data signal output circuit are controlled by a signal output from a digital delay circuit which receives the system clock signal. According to this circuit construction, the hold time between the change in the system clock and the change in the address and data signals is determined by the delay circuit which exhibits a digital operation, so that the hold time can be set accurately without being affected adversely by any variation in the circuit elements due to the manufacturing process, or by temperature changes.

Abstract: An instruction is constituted by a plurality of words, minimum necessary information necessary for effective address calculation of an operand is stored in a leading word and a word or words containing an operation specification field (operation words) are arranged to continue the first word. According to this system, the operation word can be decoded concurrently with the address calculation of the operand or the operand fetch operation. Therefore, there is no need to secure a time exclusively for decoding the operation word and the execution speed of the instruction requiring the operand can be improved.

Abstract: An instruction is constituted by a plurality of words, minimum necessary information necessary for effective address calculation of an operand is stored in a leading word and a word or words containing an operation specification field (operation words) are arranged to continue the first word. According to this system, the operation word can be decoded concurrently with the address calculation of the operand or the operand fetch operation. Therefore, there is no need to secure a time exclusively for decoding the operation word and the execution speed of the instruction requiring the operand can be improved.

Abstract: An instruction having two operands includes a field specifying the bit length of a source operand and a field specifying the bit length of data to be operated upon by the execution unit. Based on size information stored in these fields, the operand bit length is modified, which avoids need for modification of the bit length of an operand by use of a macro instruction at the time of execution of an operation based on the two operands. Consequently, the program execution speed can be improved.