Abstract: The present invention enables an unaligned access of a DMA controller to be dealt at the time of obtaining trace data. A DMA controller receives a DMA request and accesses a memory via a bus on a predetermined access unit basis in accordance with the received DMA request. When the DMA request indicates “read”, a trace interface outputs the data obtained from the memory by the DMA controller, a start address designated by the DMA request, and valid transfer size in the data obtained from the memory to a trace circuit. The trace circuit stores data of the amount of the valid transfer size from the start address designated by the DMA request in the data obtained from the memory into the trace buffer.

Abstract: The present invention enables an unaligned access of a DMA controller to be dealt at the time of obtaining trace data. A DMA controller receives a DMA request and accesses a memory via a bus on a predetermined access unit basis in accordance with the received DMA request. When the DMA request indicates “read”, a trace interface outputs the data obtained from the memory by the DMA controller, a start address designated by the DMA request, and valid transfer size in the data obtained from the memory to a trace circuit. The trace circuit stores data of the amount of the valid transfer size from the start address designated by the DMA request in the data obtained from the memory into the trace buffer.

Abstract: A memory control system includes a first memory for accessing a CPU via an address bus and a data bus, an SDRAM for accessing a CPU via the address bus and the data bus, a SDRAM control circuit for outputting a refresh request to the DRAM and a selection unit for selecting a signal line of the address bus and outputting a signal of the signal line corresponding to the refresh request of the SDRAM control circuit to the SDRAM.

Abstract: A memory control system includes a first memory for accessing a CPU via an address bus and a data bus, an SDRAM for accessing a CPU via the address bus and the data bus, a SDRAM control circuit for outputting a refresh request to the DRAM and a selection unit for selecting a signal line of the address bus and outputting a signal of the signal line corresponding to the refresh request of the SDRAM control circuit to the SDRAM.

Abstract: In an automatic frequency control circuit, a circuit constitution thereof is simplified without decreasing performance of demodulation. In the control circuit, a frequency counter counts a number of regenerative intermediate frequency from an intermediate frequency or a wave detection circuit, then a magnitude comparator compares an output of the frequency counter with a prescribed comparison data, before a subtraction circuit subtracts the output of the frequency counter from the prescribed comparison data. An operation part implements required operation according to an output of the magnitude comparator and an output of the subtraction circuit. A D/A converter converts an output data of the operation part into an analog signal. A TCXO oscillates an oscillation frequency according to the analog signal of the D/A converter. A variable frequency demultiplier is connected to a stage in front of the frequency counter.

Abstract: A digital and analog modulator is configured in a simplified circuit structure. The modulator includes a first frequency mixer circuit for modulating a carrier with an analog signal or a sine wave component of a digital signal, a second frequency mixer circuit for modulating a signal attained by shifting a phase of the carrier with an analog signal or a cosine wave component of the digital signal, and an adder for adding signals from the first and second frequency mixer circuits to each other.