Abstract: In a video signal processor (10), a video signal is given to a video input terminal (101) via a coupling capacitor (200). A clamp circuit (104) clamps the video signal input via the video input terminal (101). A format detector section (105) detects a format of the video signal. A controller section (107) changes power supply capability of the clamp circuit (104) according to a detection result of the format detector section (105).

Abstract: A data slicer 300 includes a slice level calculation unit 310 that determines whether a detected digital video signal is a CRI signal on the basis of the amplitude of the signal, and sets a reference slice level and upper and lower slice levels which are obtained by providing offset in the reference slice level, by using only the CRI signal; a data slicing unit 160 that binarizes a digital video signal S140 using the slice levels; a decoding circuit 170 that converts binarized serial data into parallel data; and a data selection unit 320 that selects data including no error from the decoded data, and outputs the selected data through a video signal output terminal 190. Therefore, even when the video signal is distorted, this data slicer can set appropriate slice level data to binarize the video signal, thereby suppressing the occurrence rate of decoding errors.

Abstract: A band-pass filter (131), which extracts a frequency component of a teletext reference signal from a digital input signal obtained by digitizing a composite signal, is provided in a frequency characteristic enhancement circuit (130). A determination circuit (145), which determines a state of the composite signal in accordance with maximum and minimum values of an output of the frequency characteristic enhancement circuit (130) during the period of the teletext reference signal and in accordance with maximum and minimum values of the output of the frequency characteristic enhancement circuit (130) during the period of time between a current horizontal synchronization interval and a next horizontal synchronization interval, is provided in a slicing circuit (140).

Abstract: A data slice control device comprises a monotone increase detection circuit for detecting a monotone increase point of a data signal, a monotone decrease detection circuit for detecting a monotone decrease point of the data signal, a counter for calculating a monotone increase interval value from the monotone increase point to a next monotone increase point, a data holding circuit for calculating a monotone increase monotone decrease interval value from the monotone increase point to the monotone decrease point, a CRI period determination circuit for determining whether the data signal is within a CRI period or not on the basis of the monotone increase interval value and the monotone increase monotone decrease interval value, and a slice level calculation circuit for calculating a slice level from a maximum value and a minimum value of amplitude values of the data signal only when the data signal is within the CRI period.

Abstract: A data slicer 300 includes a slice level calculation unit 310 that determines whether a detected digital video signal is a CRI signal on the basis of the amplitude of the signal, and sets a reference slice level and upper and lower slice levels which are obtained by providing offset in the reference slice level, by using only the CRI signal; a data slicing unit 160 that binarizes a digital video signal S140 using the slice levels; a decoding circuit 170 that converts binarized serial data into parallel data; and a data selection unit 320 that selects data including no error from the decoded data, and outputs the selected data through a video signal output terminal 190. Therefore, even when the video signal is distorted, this data slicer can set appropriate slice level data to binarize the video signal, thereby suppressing the occurrence rate of decoding errors.

Abstract: A data slicer 300 includes a slice level calculation unit 310 that determines whether a detected digital video signal is a CRI signal on the basis of the amplitude of the signal, and sets a reference slice level and upper and lower slice levels which are obtained by providing offset in the reference slice level, by using only the CRI signal; a data slicing unit 160 that binarizes a digital video signal S140 using the slice levels; a decoding circuit 170 that converts binarized serial data into parallel data; and a data selection unit 320 that selects data including no error from the decoded data, and outputs the selected data through a video signal output terminal 190. Therefore, even when the video signal is distorted, this data slicer can set appropriate slice level data to binarize the video signal, thereby suppressing the occurrence rate of decoding errors.

Abstract: This invention provides a data signal extraction apparatus that accurately extracts data from a data signal that is serially transmitted even when phase shift or the like occurs. According to this apparatus, a phase shift amount calculation circuit 13 calculates a phase shift amount S13, then a correction amount calculation circuit 14 calculates a correction amount S14 on the basis of the phase shift amount S13, an extraction interval correction circuit 10 corrects an extraction interval value S9 on the basis of the correction amount, and an extraction pulse generation circuit 11 generates an extraction pulse S11 on the basis of a corrected extraction interval value S10, thereby extracting data from a binary signal S8 on the basis of the extraction pulse.

Abstract: A data slice control device comprises a monotone increase detection circuit for detecting a monotone increase point of a data signal, a monotone decrease detection circuit for detecting a monotone decrease point of the data signal, a counter for calculating a monotone increase interval value from the monotone increase point to a next monotone increase point, a data holding circuit for calculating a monotone increase monotone decrease interval value from the monotone increase point to the monotone decrease point, a CRI period determination circuit for determining whether the data signal is within a CRI period or not on the basis of the monotone increase interval value and the monotone increase monotone decrease interval value, and a slice level calculation circuit for calculating a slice level from a maximum value and a minimum value of amplitude values of the data signal only when the data signal is within the CRI period.

Abstract: A broadcast text data sampling apparatus comprises an A/D converter for sampling a broadcast text signal supplied from the outside, with a sampling clock of a predetermined frequency, to convert the text signal into digital data; a binarization circuit for converting the digital data into a binary signal; a sampling pulse generation circuit for detecting the cycle of clock run-in of the broadcast text signal from the binary signal, obtaining a text data sampling interval value on the basis of the clock run-in cycle, sequentially calculating the positions of data in the binary signal, which data are positioned at intervals close to the sampling interval value, starting from a predetermined sampling start position, and generating a sampling pulse that designates the calculated data positions as data sampling positions; and a sampling circuit for sampling the text data from the binary signal on the basis of the sampling pulse.

Abstract: A data slicer 300 includes a slice level calculation unit 310 that determines whether a detected digital video signal is a CRI signal on the basis of the amplitude of the signal, and sets a reference slice level and upper and lower slice levels which are obtained by providing offset in the reference slice level, by using only the CRI signal; a data slicing unit 160 that binarizes a digital video signal S140 using the slice levels; a decoding circuit 170 that converts binarized serial data into parallel data; and a data selection unit 320 that selects data including no error from the decoded data, and outputs the selected data through a video signal output terminal 190. Therefore, even when the video signal is distorted, this data slicer can set appropriate slice level data to binarize the video signal, thereby suppressing the occurrence rate of decoding errors.

Abstract: This invention provides a data signal extraction apparatus that accurately extracts data from a data signal that is serially transmitted even when phase shift or the like occurs. According to this apparatus, a phase shift amount calculation circuit 13 calculates a phase shift amount S13, then a correction amount calculation circuit 14 calculates a correction amount S14 on the basis of the phase shift amount S13, an extraction interval correction circuit 10 corrects an extraction interval value S9 on the basis of the correction amount, and an extraction pulse generation circuit 11 generates an extraction pulse S11 on the basis of a corrected extraction interval value S10, thereby extracting data from a binary signal S8 on the basis of the extraction pulse.

Abstract: A broadcast text data sampling apparatus comprises an A/D converter for sampling a broadcast text signal supplied from the outside, with a sampling clock of a predetermined frequency, to convert the text signal into digital data; a binarization circuit for converting the digital data into a binary signal; a sampling pulse generation circuit for detecting the cycle of clock run-in of the broadcast text signal from the binary signal, obtaining a text data sampling interval value on the basis of the clock run-in cycle, sequentially calculating the positions of data in the binary signal, which data are positioned at intervals close to the sampling interval value, starting from a predetermined sampling start position, and generating a sampling pulse that designates the calculated data positions as data sampling positions; and a sampling circuit for sampling the text data from the binary signal on the basis of the sampling pulse.

Abstract: A progressive scanning conversion apparatus for converting an interlaced scan video signal into a progressive scan video signal by performing interpolation based on original pixels which are obtained in a matrix by sampling the interlaced scan video signal in a current field, original pixels which are obtained in a matrix by sampling the interlaced scan video signal in a previous field which is immediately prior to the current field, and original pixels which are obtained in a matrix by sampling the interlaced scan video signal in a next field which is immediately following the current field.

Abstract: A progressive scanning conversion apparatus for converting an interlaced scan video signal into a progressive scan video signal by performing interpolation based on original pixels which are obtained in a matrix by sampling the interlaced scan video signal in a current field, original pixels which are obtained in a matrix by sampling the interlaced scan video signal in a previous field which is immediately prior to the current field, and original pixels which are obtained in a matrix by sampling the interlaced scan video signal in a next field which is immediately following the current field.