Patents by Inventor Keiichi Matsushita
Keiichi Matsushita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190198655Abstract: A semiconductor device includes a substrate: a first nitride semiconductor layer formed on the substrate; a second nitride semiconductor layer formed on the first nitride semiconductor layer and containing a gallium element; a source electrode and a drain electrode formed on the second nitride semiconductor layer and contacting the second nitride semiconductor layer; a third nitride semiconductor layer formed on the second nitride semiconductor layer and containing an indium element and an aluminum element; and a gate electrode formed on the third nitride semiconductor layer and formed between the source electrode and the drain electrode.Type: ApplicationFiled: June 28, 2018Publication date: June 27, 2019Applicants: Kabushiki Kaisha Toshiba, Toshiba Infrastructure Systems & Solutions CorporationInventor: Keiichi MATSUSHITA
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Publication number: 20180277650Abstract: A semiconductor device includes a semiconductor layer provided on a substrate, a drain electrode and a source electrode provided on the semiconductor layer, and a gate electrode provided on the semiconductor layer such that an angle between a lateral surface and the semiconductor layer gradually decreases toward the semiconductor layer.Type: ApplicationFiled: January 23, 2018Publication date: September 27, 2018Applicants: Kabushiki Kaisha Toshiba, Toshiba Infrastructure Systems & Solutions CorporationInventor: Keiichi MATSUSHITA
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Publication number: 20170256626Abstract: A semiconductor device includes a substrate, a nitride semiconductor layer formed on the substrate, a gate electrode formed on the nitride semiconductor layer; and a silicon nitride layer which coats the gate electrode and is formed on the nitride semiconductor layer, wherein the silicon nitride layer has a refractive index of less than 1.9 at the nitride semiconductor layer side.Type: ApplicationFiled: October 21, 2016Publication date: September 7, 2017Applicant: Kabushiki Kaisha ToshibaInventor: Keiichi MATSUSHITA
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Publication number: 20170054013Abstract: A semiconductor device includes a substrate; a first nitride semiconductor layer formed on the substrate, a second nitride semiconductor layer formed on the first nitride semiconductor layer and containing gallium element; and a third nitride semiconductor layer formed on the second nitride semiconductor layer and containing indium element, aluminum element, and gallium element, in which the composition ratio of the gallium element of the third nitride semiconductor layer is a proportion smaller than that of the second nitride semiconductor layer.Type: ApplicationFiled: August 8, 2016Publication date: February 23, 2017Applicant: Kabushiki Kaisha ToshibaInventor: Keiichi MATSUSHITA
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Patent number: 9508809Abstract: A semiconductor device includes a substrate, a semiconductor layer having a buffer layer, a spacer layer, and barrier layer sequentially stacked on the substrate, and first and second ohmic electrodes installed on an upper surface of the barrier layer in the substrate to be separated from each other. Each of the first and second ohmic electrodes includes a portion formed on the upper surface of the barrier layer and electrode portions filling a plurality of grooves penetrating from the upper surface of the barrier layer through the barrier layer and the spacer layer and reaching a region of a two-dimensional electron gas layer formed in a spacer-layer side of the buffer layer, the electrode portions being in contact with side walls of each of the plurality of the grooves, and the portion formed on the upper surface of the barrier layer and the electrode portions are integrally formed.Type: GrantFiled: July 6, 2015Date of Patent: November 29, 2016Assignee: Kabushiki Kaisha ToshibaInventor: Keiichi Matsushita
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Publication number: 20160071939Abstract: A semiconductor device includes a substrate, a semiconductor layer having a buffer layer, a spacer layer, and barrier layer sequentially stacked on the substrate, and first and second ohmic electrodes installed on an upper surface of the barrier layer in the substrate to be separated from each other. Each of the first and second ohmic electrodes includes a portion formed on the upper surface of the barrier layer and electrode portions filling a plurality of grooves penetrating from the upper surface of the barrier layer through the barrier layer and the spacer layer and reaching a region of a two-dimensional electron gas layer formed in a spacer-layer side of the buffer layer, the electrode portions being in contact with side walls of each of the plurality of the grooves, and the portion formed on the upper surface of the barrier layer and the electrode portions are integrally formed.Type: ApplicationFiled: July 6, 2015Publication date: March 10, 2016Applicant: Kabushiki Kaisha ToshibaInventor: Keiichi MATSUSHITA
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Publication number: 20150279924Abstract: An MIM capacitor includes a lower electrode on a surface of a semiconductor substrate, an insulating film on the surface of the semiconductor substrate and a portion of the lower electrode, an upper electrode on a surface of a portion of the insulating film above the lower electrode, and an air bridge wire connected only to a central region of a surface of the upper electrode so as to be spaced above an end region of the surface of the upper electrode.Type: ApplicationFiled: March 26, 2015Publication date: October 1, 2015Inventor: Keiichi MATSUSHITA
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Patent number: 9099425Abstract: According to one embodiment, a semiconductor device includes a semiconductor element, a mounting member including Cu, and a bonding layer provided between the semiconductor element and the mounting member. The bonding layer includes a first region including Ti and Cu, and a second region provided between the first region and the mounting member, and including Sn and Cu. A first position along the first direction is positioned between the semiconductor element and a second position along the first direction. The first position is where the composition ratio of Ti in the first region is 0.1 times a maximum value of the composition ratio of Ti. The second position is where the composition ratio of Sn in the second region is 0.1 times a maximum value of the composition ratio of Sn. A distance between the first position and the second position is not less than 0.1 micrometers.Type: GrantFiled: July 2, 2014Date of Patent: August 4, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Keiichi Matsushita, Yo Sasaki
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Publication number: 20150069597Abstract: According to one embodiment, a semiconductor device includes a semiconductor element, a mounting member including Cu, and a bonding layer provided between the semiconductor element and the mounting member. The bonding layer includes a first region including Ti and Cu, and a second region provided between the first region and the mounting member, and including Sn and Cu. A first position along the first direction is positioned between the semiconductor element and a second position along the first direction. The first position is where the composition ratio of Ti in the first region is 0.1 times a maximum value of the composition ratio of Ti. The second position is where the composition ratio of Sn in the second region is 0.1 times a maximum value of the composition ratio of Sn. A distance between the first position and the second position is not less than 0.1 micrometers.Type: ApplicationFiled: July 2, 2014Publication date: March 12, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Keiichi MATSUSHITA, Yo SASAKI
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Patent number: 8614460Abstract: A semiconductor device and a fabrication method of the semiconductor device, the semiconductor device including: a substrate; a nitride based compound semiconductor layer placed on the substrate and doped with a first transition metal atom; an aluminum gallium nitride layer (AlxGa1-xN) (where 0.1<=x<=1) placed on the nitride based compound semiconductor layer; a nitride based compound semiconductor layer placed on the aluminum gallium nitride layer (AlxGa1-xN) (where 0.1<=x<=1) and doped with a second transition metal atom; an aluminum gallium nitride layer (AlyGa1-yN) (where 0.1<=y<=1) placed on the nitride based compound semiconductor layer doped with the second transition metal atom; and a gate electrode, a source electrode, and a drain electrode which are placed on the aluminum gallium nitride layer (AlyGa1-yN) (where 0.1<=y<=1).Type: GrantFiled: January 30, 2012Date of Patent: December 24, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Keiichi Matsushita
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Patent number: 8482354Abstract: A power amplifying device includes earth parts which are connected with via holes for grounding, source electrode earth conductors which connect the earth parts, source electrodes which are coupled to the source electrode earth conductors, an inner source electrode which is not in contact with the source electrode earth conductors, a drain electrode, a gate electrode and an air bridge which directly connects the inner source electrode and earth parts.Type: GrantFiled: July 28, 2011Date of Patent: July 9, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Keiichi Matsushita
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Patent number: 8445341Abstract: A semiconductor device includes a substrate; a nitride based compound semiconductor layer placed on the substrate; an active area which is placed on the nitride based compound semiconductor layer, and is composed of an aluminum gallium nitride layer (AlxGa1-xN) (where 0.1<=x<=1); an isolation region which performs isolation of the active area mutually; a gate electrode, a source electrode, and a drain electrode which have been placed on the active area surrounded by the isolation region; and a trench region formed by etching for a part of the active area under the gate electrode. The semiconductor device is highly reliable, high performance and high power and a fabrication method for the same is also provided.Type: GrantFiled: January 23, 2012Date of Patent: May 21, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Keiichi Matsushita
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Publication number: 20120168822Abstract: A semiconductor device and a fabrication method of the semiconductor device, the semiconductor device including: a substrate; a nitride based compound semiconductor layer placed on the substrate and doped with a first transition metal atom; an aluminum gallium nitride layer (AlxGa1-xN) (where 0.1<=x<=1) placed on the nitride based compound semiconductor layer; a nitride based compound semiconductor layer placed on the aluminum gallium nitride layer (AlxGa1-xN) (where 0.1<=x<=1) and doped with a second transition metal atom; an aluminum gallium nitride layer (AlyGa1-yN) (where 0.1<=y<=1) placed on the nitride based compound semiconductor layer doped with the second transition metal atom; and a gate electrode, a source electrode, and a drain electrode which are placed on the aluminum gallium nitride layer (AlyGa1-yN) (where 0.1<=y<=1).Type: ApplicationFiled: January 30, 2012Publication date: July 5, 2012Applicant: Kabushiki Kaisha ToshibaInventor: Keiichi MATSUSHITA
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Publication number: 20120133440Abstract: A power amplifying device includes earth parts which are connected with via holes for grounding, source electrode earth conductors which connect the earth parts, source electrodes which are coupled to the source electrode earth conductors, an inner source electrode which is not in contact with the source electrode earth conductors, a drain electrode, a gate electrode and an air bridge which directly connects the inner source electrode and earth parts.Type: ApplicationFiled: July 28, 2011Publication date: May 31, 2012Applicant: Kabushiki Kaisha ToshibaInventor: Keiichi MATSUSHITA
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Publication number: 20120119226Abstract: A semiconductor device includes a substrate; a nitride based compound semiconductor layer placed on the substrate; an active area which is placed on the nitride based compound semiconductor layer, and is composed of an aluminum gallium nitride layer (AlxGa1-xN) (where 0.1<=x<=1); an isolation region which performs isolation of the active area mutually; a gate electrode, a source electrode, and a drain electrode which have been placed on the active area surrounded by the isolation region; and a trench region formed by etching for a part of the active area under the gate electrode. The semiconductor device is highly reliable, high performance and high power and a fabrication method for the same is also provided.Type: ApplicationFiled: January 23, 2012Publication date: May 17, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Keiichi MATSUSHITA
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Patent number: 8178899Abstract: A semiconductor device and a fabrication method of the semiconductor device, the semiconductor device including: a substrate; a nitride based compound semiconductor layer placed on the substrate and doped with a first transition metal atom; an aluminum gallium nitride layer (AlxGa1?xN) (where 0.1<=x<=1) placed on the nitride based compound semiconductor layer; a nitride based compound semiconductor layer placed on the aluminum gallium nitride layer (AlxGa1?xN) (where 0.1<=x<=1) and doped with a second transition metal atom; an aluminum gallium nitride layer (AlyGa1?yN) (where 0.1<=y<=1) placed on the nitride based compound semiconductor layer doped with the second transition metal atom; and a gate electrode, a source electrode, and a drain electrode which are placed on the aluminum gallium nitride layer (AlyGa1?yN) (where 0.1<=y<=1).Type: GrantFiled: November 13, 2008Date of Patent: May 15, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Keiichi Matsushita
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Patent number: 8154079Abstract: A semiconductor device, which can prevent an element breakdown by alleviating of electric field concentrations, and can also prevent reduction of gain, includes: a source electrode formed on a semiconductor layer; a drain electrode formed on the semiconductor layer; a gate electrode formed between the source electrode and the drain electrode; an insulating film formed on the semiconductor layer and the gate electrode; a field plate electrode formed on the insulating film; and a resistor for connecting the field plate electrode and the source electrode.Type: GrantFiled: November 28, 2007Date of Patent: April 10, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Keiichi Matsushita, Kazutaka Takagi, Naotaka Tomita
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Patent number: 8133776Abstract: A semiconductor device includes a substrate; a nitride based compound semiconductor layer placed on the substrate; an active area which is placed on the nitride based compound semiconductor layer, and is composed of an aluminum gallium nitride layer (AlxGa1-xN) (where 0.1<=x<=1); an isolation region which performs isolation of the active area mutually; a gate electrode, a source electrode, and a drain electrode which have been placed on the active area surrounded by the isolation region; and a trench region formed by etching for a part of the active area under the gate electrode. The semiconductor device is highly reliable, high performance and high power and a fabrication method for the same is also provided.Type: GrantFiled: April 2, 2009Date of Patent: March 13, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Keiichi Matsushita
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Patent number: 7915747Abstract: A substrate for forming a semiconductor layer includes a plurality of linear convexes or grooves on a surface of the substrate by crystal growth. The plurality of linear convexes or grooves are formed along a direction of a cleavage plane of the semiconductor layer.Type: GrantFiled: June 27, 2006Date of Patent: March 29, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Keiichi Matsushita
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Publication number: 20100052014Abstract: A semiconductor device includes a substrate; a nitride based compound semiconductor layer placed on the substrate; an active area which is placed on the nitride based compound semiconductor layer, and is composed of an aluminum gallium nitride layer (AlxGa1-xN) (where 0.1<=x<=1); an isolation region which performs isolation of the active area mutually; a gate electrode, a source electrode, and a drain electrode which have been placed on the active area surrounded by the isolation region; and a trench region formed by etching for a part of the active area under the gate electrode. The semiconductor device is highly reliable, high performance and high power and a fabrication method for the same is also provided.Type: ApplicationFiled: April 2, 2009Publication date: March 4, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Keiichi MATSUSHITA