Patents by Inventor Keiichi Nishimuda

Keiichi Nishimuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor integrated circuit with multi-cut via and automated layout method for the same
    Patent number: 8418109
    Abstract: A semiconductor integrated circuit includes a first wiring, a second wiring, a third wiring, a fourth wiring, a first overlap area, a second overlap area, a multi-cut via, the multi-cut via including a first via and a second via formed in the first direction, and a single-cut via formed to connect the third wiring to the fourth wiring in the second overlap area. A width of the second portion of the second wiring corresponding to a first direction is longer than a width of the first portion of the second wiring corresponding to the first direction. A distance between the center of the first via and the center of the second via is longer than the width of the first portion of second wiring.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: April 9, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Keiichi Nishimuda
  • SEMICONDUCTOR INTEGRATED CIRCUIT WITH MULTI-CUT VIA AND AUTOMATED LAYOUT METHOD FOR THE SAME
    Publication number: 20120306083
    Abstract: A semiconductor integrated circuit includes a first wiring, a second wiring, a third wiring, a fourth wiring, a first overlap area, a second overlap area, a multi-cut via, the multi-cut via including a first via and a second via formed in the first direction, and a single-cut via formed to connect the third wiring to the fourth wiring in the second overlap area. A width of the second portion of the second wiring corresponding to a first direction is longer than a width of the first portion of the second wiring corresponding to the first direction. A distance between the center of the first via and the center of the second via is longer than the width of the first portion of second wiring.
    Type: Application
    Filed: August 15, 2012
    Publication date: December 6, 2012
    Applicant: Renesas Electronics Corporation
    Inventor: Keiichi NISHIMUDA
  • Semiconductor integrated circuit with multi-cut via and automated layout method for the same
    Patent number: 8271926
    Abstract: A semiconductor integrated circuit includes a first wiring formed on a first wiring layer and prolonged in a first direction, a second wiring formed on a second wiring layer and prolonged in a second direction, a third wiring formed on the first wiring layer and prolonged in the first direction, a fourth wiring formed on the second wiring layer and prolonged in the second direction, a multi-cut via formed to connect the first wiring to the second wiring, the multi-cut via including a first via and a second via formed in the first direction, and a single-cut via formed to connect the third wiring to the fourth wiring. A first overhang is provided in a direction opposite to the first direction, the first overhang being larger than a second overhang, the second overhang being smaller than a third overhang.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: September 18, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Keiichi Nishimuda
  • Semiconductor integrated circuit with multi-cut via and automated layout method for the same
    Publication number: 20110304055
    Abstract: A semiconductor integrated circuit includes a first wiring formed on a first wiring layer and prolonged in a first direction, a second wiring formed on a second wiring layer and prolonged in a second direction, a third wiring formed on the first wiring layer and prolonged in the first direction, a fourth wiring formed on the second wiring layer and prolonged in the second direction, a multi-cut via formed to connect the first wiring to the second wiring, the multi-cut via including a first via and a second via formed in the first direction, and a single-cut via formed to connect the third wiring to the fourth wiring. A first overhang is provided in a direction opposite to the first direction, the first overhang being larger than a second overhang, the second overhang being smaller than a third overhang.
    Type: Application
    Filed: August 17, 2011
    Publication date: December 15, 2011
    Applicant: Renesas Electronics Corporation
    Inventor: Keiichi Nishimuda
  • Semiconductor integrated circuit with multi-cut via and automated layout method for the same
    Patent number: 8020133
    Abstract: A semiconductor integrated circuit according to an embodiment of the invention includes a single-cut via 60 and a multi-cut via 30 that includes a first via 30a and a second via 30b. An overhang (OHa or OHb) with respect to at least one of the first via 30a and the second via 30b is smaller than an overhang OH with respect to the single-cut via 60.
    Type: Grant
    Filed: March 20, 2008
    Date of Patent: September 13, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Keiichi Nishimuda
  • Semiconductor integrated circuit with multi-cut via and automated layout method for the same
    Publication number: 20080235644
    Abstract: A semiconductor integrated circuit according to an embodiment of the invention includes a single-cut via 60 and a multi-cut via 30 that includes a first via 30a and a second via 30b. An overhang (OHa or OHb) with respect to at least one of the first via 30a and the second via 30b is smaller than an overhang OH with respect to the single-cut via 60.
    Type: Application
    Filed: March 20, 2008
    Publication date: September 25, 2008
    Applicant: NEC Electronics Corporation
    Inventor: Keiichi Nishimuda