Patents by Inventor Keiichi NIWA

Keiichi NIWA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230411269
    Abstract: According to one embodiment, a wiring board, includes a conductive layer on a first surface and an insulating layer covering a portion of the conductive layer. The conductive layer includes a first connection portion exposed from the insulating layer and having a first wettability to solder, a lead-out portion connected to the first connection portion and exposed from the insulating layer and having a second wettability to solder, and a wiring portion connected to the first connection portion via the lead-out portion and covered with the insulating layer. In some examples, the first connection portion may be coated with a gold layer and the conductive layer may be copper or a copper alloy material.
    Type: Application
    Filed: March 2, 2023
    Publication date: December 21, 2023
    Inventor: Keiichi NIWA
  • Patent number: 11837569
    Abstract: A semiconductor device according to the present embodiment includes a circuit board comprising a plurality of electrodes provided on a first surface, a first resin layer provided on the first surface around the electrodes, and a second resin layer provided on the first resin layer. A first semiconductor chip is connected to a first one of the electrodes. A second semiconductor chip is provided above the first semiconductor chip, being larger than the first semiconductor chip, and is connected to a second one of the electrodes via a metal wire. A third resin layer is provided between the first semiconductor chip and the second semiconductor chip and between the second resin layer and the second semiconductor chip, and covers the first semiconductor chip.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: December 5, 2023
    Assignee: Kioxia Corporation
    Inventors: Yoshiharu Okada, Masatoshi Kawato, Keiichi Niwa
  • Patent number: 11804464
    Abstract: A semiconductor device includes a wiring board; a first semiconductor chip including a first surface, a second surface, and a connection bump on the first surface, the first semiconductor chip coupled to the wiring board through the connection bump; a resin layer covering the connection bump between the first semiconductor chip and the wiring board, an upper surface of the resin layer parallel to the second surface of the first semiconductor chip; and a second semiconductor chip including a third surface, a fourth surface, and an adhesive layer on the third surface, the second semiconductor chip adhering to the second surface of the first semiconductor chip and the upper surface of the resin layer through the adhesive layer. The upper surface of the resin layer projects outside a portion of at least an outer edge of the second semiconductor chip when viewed from the top.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: October 31, 2023
    Assignee: KIOXIA CORPORATION
    Inventor: Keiichi Niwa
  • Publication number: 20230170321
    Abstract: A semiconductor device includes a substrate having a first surface, a second surface opposite to the first surface, conductive connections provided on the first surface, and columnar electrodes each extending from a corresponding one of the conductive connections toward the second surface, each of the columnar electrodes having a tapered shape; and a semiconductor chip having a third surface facing the first surface and a plurality of connection bumps provided on the third surface, each of the plurality of connection bumps electrically connected to a corresponding one of the plurality of conductive connections. A first one of the columnar electrodes, located in a first region of a chip region, has a first tapered shape. A second one of the columnar electrodes, located in a second region of the chip region, has a second tapered shape different from the first tapered shape.
    Type: Application
    Filed: August 25, 2022
    Publication date: June 1, 2023
    Applicant: KIOXIA CORPORATION
    Inventor: Keiichi NIWA
  • Publication number: 20230022159
    Abstract: A semiconductor device includes: a substrate on which wiring is formed; a first semiconductor element flip-chip bonded to the substrate; a second semiconductor element provided on the first semiconductor element; a first resin provided in at least part of a region between the first semiconductor element and the substrate; a second resin provided in at least part of a region between the second semiconductor element and the substrate; and a member having a thermal conductivity higher than a thermal conductivity of the first resin and a thermal conductivity of the second resin, provided between the first resin and the second resin, having a part overlapping with an upper surface of the first semiconductor element, and having another part overlapping with a first wiring part as part of the wiring in a top view.
    Type: Application
    Filed: March 10, 2022
    Publication date: January 26, 2023
    Applicant: Kioxia Corporation
    Inventors: Keiichi NIWA, Yoshiaki GOTO
  • Patent number: 11482502
    Abstract: A semiconductor device includes a substrate that includes a first insulating layer, a conductive layer on the first insulating layer, a second insulating layer on the conductive layer, and an opening that passes through the conductive layer and the second insulating layer and in which part of the conductive layer is exposed, a conductive material that contacts at least the first insulating layer and the part of the conductive layer in the opening, and a semiconductor chip that has an electrode extending towards the first insulating layer within the opening and contacting the conductive material.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: October 25, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Keiichi Niwa
  • Publication number: 20220059493
    Abstract: A semiconductor device according to the present embodiment includes a circuit board comprising a plurality of electrodes provided on a first surface, a first resin layer provided on the first surface around the electrodes, and a second resin layer provided on the first resin layer. A first semiconductor chip is connected to a first one of the electrodes. A second semiconductor chip is provided above the first semiconductor chip, being larger than the first semiconductor chip, and is connected to a second one of the electrodes via a metal wire. A third resin layer is provided between the first semiconductor chip and the second semiconductor chip and between the second resin layer and the second semiconductor chip, and covers the first semiconductor chip.
    Type: Application
    Filed: February 18, 2021
    Publication date: February 24, 2022
    Applicant: Kioxia Corporation
    Inventors: Yoshiharu OKADA, Masatoshi KAWATO, Keiichi NIWA
  • Publication number: 20220005779
    Abstract: A semiconductor device includes a wiring board; a first semiconductor chip including a first surface, a second surface, and a connection bump on the first surface, the first semiconductor chip coupled to the wiring board through the connection bump; a resin layer covering the connection bump between the first semiconductor chip and the wiring board, an upper surface of the resin layer parallel to the second surface of the first semiconductor chip; and a second semiconductor chip including a third surface, a fourth surface, and an adhesive layer on the third surface, the second semiconductor chip adhering to the second surface of the first semiconductor chip and the upper surface of the resin layer through the adhesive layer. The upper surface of the resin layer projects outside a portion of at least an outer edge of the second semiconductor chip when viewed from the top.
    Type: Application
    Filed: March 3, 2021
    Publication date: January 6, 2022
    Inventor: Keiichi NIWA
  • Patent number: 11211361
    Abstract: According to one embodiment, a semiconductor device includes a first substrate. A first semiconductor chip having a first surface facing the first substrate and a second surface opposite the first surface. The first semiconductor chip has electrodes on the first surface and is coupled to the first substrate. A first resin layer is provided at least between the first substrate and the first semiconductor chip, and covers the second surface. The first resin layer has an upper surface substantially flatter than the second surface.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: December 28, 2021
    Assignee: Kioxia Corporation
    Inventor: Keiichi Niwa
  • Publication number: 20210249373
    Abstract: A semiconductor device includes a substrate that includes a first insulating layer, a conductive layer on the first insulating layer, a second insulating layer on the conductive layer, and an opening that passes through the conductive layer and the second insulating layer and in which part of the conductive layer is exposed, a conductive material that contacts at least the first insulating layer and the part of the conductive layer in the opening, and a semiconductor chip that has an electrode extending towards the first insulating layer within the opening and contacting the conductive material.
    Type: Application
    Filed: August 31, 2020
    Publication date: August 12, 2021
    Inventor: Keiichi NIWA
  • Patent number: 10964658
    Abstract: A semiconductor device according to an embodiment includes a substrate. An insulating film is provided above the substrate. Electrode pads are provided on the insulating film. Metallic bumps are respectively provided on surfaces of the electrode pads. A sidewall film comprises a metallic oxide or a metallic hydroxide provided on side surfaces of the metallic bumps. A barrier metal layer comprises first portions each provided between one of the metallic bumps and a corresponding one of the electrode pads and comprising a metal, and second portions provided at least on the electrode pads at a periphery of the metallic bumps and comprising a metallic oxide or a metallic hydroxide.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: March 30, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Keiichi Niwa
  • Publication number: 20210066249
    Abstract: According to one embodiment, a semiconductor device includes a first substrate. A first semiconductor chip having a first surface facing the first substrate and a second surface opposite the first surface. The first semiconductor chip has electrodes on the first surface and is coupled to the first substrate. A first resin layer is provided at least between the first substrate and the first semiconductor chip, and covers the second surface. The first resin layer has an upper surface substantially flatter than the second surface.
    Type: Application
    Filed: March 3, 2020
    Publication date: March 4, 2021
    Applicant: KIOXIA CORPORATION
    Inventor: Keiichi NIWA
  • Patent number: 10892240
    Abstract: A semiconductor fabrication apparatus has a transfer plate having a plurality of transfer pins to transfer a flux onto a plurality of lands on a semiconductor substrate, a holder movable with the transfer plate, to hold the transfer plate, a positioning mechanism to perform positioning of the holder so that the plurality of lands and the respective transfer pins contact each other; and a pitch adjuster to adjust a pitch of at least part of the plurality of transfer pins.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: January 12, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Keiichi Niwa
  • Publication number: 20200266168
    Abstract: A semiconductor device according to an embodiment includes a substrate. An insulating film is provided above the substrate. Electrode pads are provided on the insulating film. Metallic bumps are respectively provided on surfaces of the electrode pads. A sidewall film comprises a metallic oxide or a metallic hydroxide provided on side surfaces of the metallic bumps. A barrier metal layer comprises first portions each provided between one of the metallic bumps and a corresponding one of the electrode pads and comprising a metal, and second portions provided at least on the electrode pads at a periphery of the metallic bumps and comprising a metallic oxide or a metallic hydroxide.
    Type: Application
    Filed: August 27, 2019
    Publication date: August 20, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Keiichi NIWA
  • Publication number: 20190295976
    Abstract: A semiconductor fabrication apparatus has a transfer plate having a plurality of transfer pins to transfer a flux onto a plurality of lands on a semiconductor substrate, a holder movable with the transfer plate, to hold the transfer plate, a positioning mechanism to perform positioning of the holder so that the plurality of lands and the respective transfer pins contact each other; and a pitch adjuster to adjust a pitch of at least part of the plurality of transfer pins.
    Type: Application
    Filed: September 10, 2018
    Publication date: September 26, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Keiichi NIWA