Patents by Inventor Keiichi Sakuno

Keiichi Sakuno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11177800
    Abstract: A power transmission device is provided that enables more accurate detection of an undesired switching state for a switching element and an appropriate supply of power. The power transmission device includes a power supply, a switching element, a ringing detection circuit, and a control circuit unit. The ringing detection circuit detects ringing that occurs in the switching element. The control circuit unit controls at least the power supply or the switching element in accordance with a detection result of the ringing detection circuit. The ringing detection circuit includes a diode and a resistor. The diode conducts when a negative polarity voltage is generated in the switching element. The resistor is connected in series with the diode.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: November 16, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Masato Sasaki, Keiichi Sakuno
  • Publication number: 20210091765
    Abstract: A power transmission device is provided that enables more accurate detection of an undesired switching state for a switching element and an appropriate supply of power. The power transmission device includes a power supply, a switching element, a ringing detection circuit, and a control circuit unit. The ringing detection circuit detects ringing that occurs in the switching element. The control circuit unit controls at least the power supply or the switching element in accordance with a detection result of the ringing detection circuit. The ringing detection circuit includes a diode and a resistor. The diode conducts when a negative polarity voltage is generated in the switching element. The resistor is connected in series with the diode.
    Type: Application
    Filed: December 3, 2018
    Publication date: March 25, 2021
    Inventors: MASATO SASAKI, KEIICHI SAKUNO
  • Patent number: 9882499
    Abstract: In a switching power supply circuit of the invention, a low-voltage node capacitor is connected between a primary-side low-voltage stable potential node and a secondary-side low-voltage stable potential node, and a high-voltage node capacitor is connected between a primary-side high-voltage stable potential node and an anode of a rectifier element. Thereby, it is possible to provide the switching power supply circuit which achieves, with a simple configuration, both of noise reduction and potential stabilization of stable potential nodes.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: January 30, 2018
    Assignee: Sharp Corporation
    Inventors: Keiichi Sakuno, Hiroshi Itoh, Toshiyuki Oka
  • Publication number: 20170012548
    Abstract: In a switching power supply circuit (1A) of the invention, a low-voltage node capacitor (5) is connected between a primary-side low-voltage stable potential node (LN1) and a secondary-side low-voltage stable potential node (LN2), and a high-voltage node capacitor (4) is connected between a primary-side high-voltage stable potential node (HN1) and an anode of a rectifier element (31). Thereby, it is possible to provide the switching power supply circuit which achieves, with a simple configuration, both of noise reduction and potential stabilization of stable potential nodes.
    Type: Application
    Filed: January 8, 2015
    Publication date: January 12, 2017
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Keiichi SAKUNO, Hiroshi ITOH, Toshiyuki OKA
  • Patent number: 8766275
    Abstract: This composite semiconductor device has a normally-on first field effect transistor and a normally-off second field effect transistor connected in series between first and second terminals, gates of the first and second field effect transistors being connected to second and third terminals, respectively, and N diodes being connected in series in a forward direction between a drain and a source of the second field effect transistor. Therefore, a drain-source voltage (Vds) of the second field effect transistor can be restricted to a voltage not higher than a withstand voltage of the second field effect transistor.
    Type: Grant
    Filed: December 28, 2010
    Date of Patent: July 1, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Naoyasu Iketani, Tomohiro Nozawa, Yoshiaki Nozaki, John K. Twynam, Hiroshi Kawamura, Keiichi Sakuno
  • Publication number: 20120292635
    Abstract: This composite semiconductor device has a normally-on first field effect transistor and a normally-off second field effect transistor connected in series between first and second terminals, gates of the first and second field effect transistors being connected to second and third terminals, respectively, and N diodes being connected in series in a forward direction between a drain and a source of the second field effect transistor. Therefore, a drain-source voltage (Vds) of the second field effect transistor can be restricted to a voltage not higher than a withstand voltage of the second field effect transistor.
    Type: Application
    Filed: December 28, 2010
    Publication date: November 22, 2012
    Inventors: Naoyasu Iketani, Tomohiro Nozawa, Yoshiaki Nozaki, John K. Twynam, Hiroshi Kawamura, Keiichi Sakuno
  • Patent number: 7173487
    Abstract: A power amplification circuit, and a communication device using the same, which are capable of suppressing gain decreases of a power amplifier due to increases in input signal power in a state near the saturation operation, capable of reducing its size, and low in distortion and high in efficiency. The power amplification circuit includes a power amplifier and a negative feedback circuit connected between a signal input terminal and a signal output terminal of the power amplifier. Impedance of the negative feedback circuit depends on a signal voltage occurring across the negative feedback circuit. By adjusting the characteristic that the negative feedback quantity of the negative feedback circuit to the power amplifier is variable depending on input signal power, gain fluctuations of the power amplifier due to increases or decreases of input signal power or output signal power around a specified output signal power are suppressed.
    Type: Grant
    Filed: November 13, 2003
    Date of Patent: February 6, 2007
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Keiichi Sakuno
  • Patent number: 6873207
    Abstract: A power amplification circuit, and a communication device using the same, which are capable of suppressing gain decreases of a power amplifier due to increases in input signal power in a state near the saturation operation, capable of reducing its size, and low in distortion and high in efficiency. The power amplification circuit includes a power amplifier and a negative feedback circuit connected between a signal input terminal and a signal output terminal of the power amplifier. Impedance of the negative feedback circuit depends on a signal voltage occurring across the negative feedback circuit. By adjusting the characteristic that the negative feedback quantity of the negative feedback circuit to the power amplifier is variable depending on input signal power, gain fluctuations of the power amplifier due to increases or decreases of input signal power or output signal power around a specified output signal power are suppressed.
    Type: Grant
    Filed: November 27, 2001
    Date of Patent: March 29, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Keiichi Sakuno
  • Patent number: 6806774
    Abstract: A resistor and a capacitor are provided for a variable impedance element which performs distortion compensation of a power amplifier. Thus, compensation of amplitude-amplitude distortion and amplitude-phase distortion can be separately adjusted. As a result, distortion of the power amplifier can be reduced effectively and a highly efficient operation is made possible.
    Type: Grant
    Filed: July 2, 2002
    Date of Patent: October 19, 2004
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Keiichi Sakuno
  • Publication number: 20040189379
    Abstract: A power amplification circuit, and a communication device using the same, which are capable of suppressing gain decreases of a power amplifier due to increases in input signal power in a state near the saturation operation, capable of reducing its size, and low in distortion and high in efficiency. The power amplification circuit includes a power amplifier and a negative feedback circuit connected between a signal input terminal and a signal output terminal of the power amplifier. Impedance of the negative feedback circuit depends on a signal voltage occurring across the negative feedback circuit. By adjusting the characteristic that the negative feedback quantity of the negative feedback circuit to the power amplifier is variable depending on input signal power, gain fluctuations of the power amplifier due to increases or decreases of input signal power or output signal power around a specified output signal power are suppressed.
    Type: Application
    Filed: November 13, 2003
    Publication date: September 30, 2004
    Applicant: Sharp Kabushiki Kaisha
    Inventor: Keiichi Sakuno
  • Patent number: 6771130
    Abstract: A power amplifier has a front and a rear stage. In the rear stage, to a base of a signal-amplifying bipolar transistor is connected one end of a variable impedance element whose impedance changes according to an input power level. An adjusting circuit is connected between the other end of the variable impedance element and a ground. A DC current adjusting element is connected between the other end of the variable impedance element and a supply voltage terminal. The front stage is made to perform class A operation or class AB operation near class A operation, while the rear stage is made to perform class B operation or class AB operation near class B operation. The distortion characteristic of the rear stage is adjusted by the variable impedance element, the adjusting circuit, and the DC current adjusting element so as to offset the distortion characteristic of the front stage.
    Type: Grant
    Filed: September 7, 2001
    Date of Patent: August 3, 2004
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Takao Hasegawa, Keiichi Sakuno
  • Publication number: 20020167358
    Abstract: A resistor and a capacitor are provided for a variable impedance element which performs distortion compensation of a power amplifier. Thus, compensation of amplitude-amplitude distortion and amplitude-phase distortion can be separately adjusted. As a result, distortion of the power amplifier can be reduced effectively and a highly efficient operation is made possible.
    Type: Application
    Filed: July 2, 2002
    Publication date: November 14, 2002
    Applicant: Sharp Kabushiki Kaisha
    Inventor: Keiichi Sakuno
  • Patent number: 6433641
    Abstract: A resistor and a capacitor are provided for a variable impedance element which performs distortion compensation of a power amplifier. Thus, compensation of amplitude-amplitude distortion and amplitude-phase distortion can be separately adjusted. As a result, distortion of the power amplifier can be reduced effectively and a highly efficient operation is made possible.
    Type: Grant
    Filed: July 18, 2000
    Date of Patent: August 13, 2002
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Keiichi Sakuno
  • Publication number: 20020093377
    Abstract: A power amplification circuit, and a communication device using the same, which are capable of suppressing gain decreases of a power amplifier due to increases in input signal power in a state near the saturation operation, capable of reducing its size, and low in distortion and high in efficiency. The power amplification circuit includes a power amplifier and a negative feedback circuit connected between a signal input terminal and a signal output terminal of the power amplifier. Impedance of the negative feedback circuit depends on a signal voltage occurring across the negative feedback circuit. By adjusting the characteristic that the negative feedback quantity of the negative feedback circuit to the power amplifier is variable depending on input signal power, gain fluctuations of the power amplifier due to increases or decreases of input signal power or output signal power around a specified output signal power are suppressed.
    Type: Application
    Filed: November 27, 2001
    Publication date: July 18, 2002
    Inventor: Keiichi Sakuno
  • Publication number: 20020033735
    Abstract: A power amplifier has a front and a rear stage. In the rear stage, to a base of a signal-amplifying bipolar transistor is connected one end of a variable impedance element whose impedance changes according to an input power level. An adjusting circuit is connected between the other end of the variable impedance element and a ground. A DC current adjusting element is connected between the other end of the variable impedance element and a supply voltage terminal. The front stage is made to perform class A operation or class AB operation near class A operation, while the rear stage is made to perform class B operation or class AB operation near class B operation. The distortion characteristic of the rear stage is adjusted by the variable impedance element, the adjusting circuit, and the DC current adjusting element so as to offset the distortion characteristic of the front stage.
    Type: Application
    Filed: September 7, 2001
    Publication date: March 21, 2002
    Inventors: Takao Hasegawa, Keiichi Sakuno
  • Patent number: 6121841
    Abstract: In a transistor power amplifier, a base of a power amplifying bipolar transistor is connected with a gain control power source via a bias resistor. The power amplifying transistor is directly biased from the gain control power source via the bias resistor, and not via a base driving bipolar transistor so as to widen an effective gain control voltage range by an amount corresponding to an ON-state voltage across a base and emitter of the base driving bipolar transistor.
    Type: Grant
    Filed: August 27, 1997
    Date of Patent: September 19, 2000
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Keiichi Sakuno