Patents by Inventor Keiichi Sawai
Keiichi Sawai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11342308Abstract: A semiconductor device is provided with a first semiconductor chip and a second semiconductor chip that are arranged so as to oppose each other. The first semiconductor chip has a first connecting portion provided in a first hole portion, and the second semiconductor chip has an electrically conductive second connecting portion that is composed of a concave metal film formed on the front surface of a second electrode portion, the side surface of a second hole portion, and the front surface of a second protective film. The first electrode portion and the second electrode portion are electrically connected via the first connecting portion and the second connecting portion.Type: GrantFiled: April 4, 2018Date of Patent: May 24, 2022Assignee: SHARP KABUSHIKI KAISHAInventor: Keiichi Sawai
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Patent number: 11145618Abstract: Bonding equipment includes a laminar flow source, a chip handling portion, a cleaning portion for cleaning a chip, a bonding portion for bonding the chip and a substrate, and a transfer mechanism for transferring the chip from the chip handling portion to the bonding portion. Among these, at least the bonding portion and the cleaning portion are disposed in a laminar flow by the laminar flow source.Type: GrantFiled: March 6, 2019Date of Patent: October 12, 2021Assignee: SHARP KABUSHIKI KAISHAInventors: Katsuji Iguchi, Masumi Maegawa, Keiichi Sawai, Hiroyoshi Higashisaka, Takanobu Matsuo
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Publication number: 20210134758Abstract: A semiconductor device is provided with a first semiconductor chip and a second semiconductor chip that are arranged so as to oppose each other. The first semiconductor chip has a first connecting portion provided in a first hole portion, and the second semiconductor chip has an electrically conductive second connecting portion that is composed of a concave metal film formed on the front surface of a second electrode portion, the side surface of a second hole portion, and the front surface of a second protective film. The first electrode portion and the second electrode portion are electrically connected via the first connecting portion and the second connecting portion.Type: ApplicationFiled: April 4, 2018Publication date: May 6, 2021Inventor: KEIICHI SAWAI
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Patent number: 10797032Abstract: In a light-emitting element module, at least two or more first electrodes of a first substrate that includes a circuit element are joined to at least two or more light-emitting elements. The first substrate includes a first wiring line to an n-th wiring line (n is an integer of 2 or more) that are formed into layers in order from the at least two or more light-emitting elements in a thickness direction of the first substrate. The first wiring line that is located in one of the layers of the first substrate nearest to the at least two or more light-emitting elements is formed at least in an interelectrode region between the adjacent first electrodes of the first substrate in a plan view.Type: GrantFiled: April 1, 2019Date of Patent: October 6, 2020Assignee: SHARP KABUSHIKI KAISHAInventors: Yuta Ikawa, Hiroyoshi Higashisaka, Tsuyoshi Ono, Keiichi Sawai
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Publication number: 20190333902Abstract: In a light-emitting element module, at least two or more first electrodes of a first substrate that includes a circuit element are joined to at least two or more light-emitting elements. The first substrate includes a first wiring line to an n-th wiring line (n is an integer of 2 or more) that are formed into layers in order from the at least two or more light-emitting elements in a thickness direction of the first substrate. The first wiring line that is located in one of the layers of the first substrate nearest to the at least two or more light-emitting elements is formed at least in an interelectrode region between the adjacent first electrodes of the first substrate in a plan view.Type: ApplicationFiled: April 1, 2019Publication date: October 31, 2019Inventors: YUTA IKAWA, HIROYOSHI HIGASHISAKA, TSUYOSHI ONO, KEIICHI SAWAI
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Publication number: 20190279956Abstract: Bonding equipment includes a laminar flow source, a chip handling portion, a cleaning portion for cleaning a chip, a bonding portion for bonding the chip and a substrate, and a transfer mechanism for transferring the chip from the chip handling portion to the bonding portion. Among these, at least the bonding portion and the cleaning portion are disposed in a laminar flow by the laminar flow source.Type: ApplicationFiled: March 6, 2019Publication date: September 12, 2019Inventors: KATSUJI IGUCHI, MASUMI MAEGAWA, KEIICHI SAWAI, HIROYOSHI HIGASHISAKA, TAKANOBU MATSUO
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Patent number: 9048407Abstract: The present invention is a method for mounting, on a ceramic substrate (9), an LED chip (1), in which an upper surface of a positive electrode (6) is in a higher position than an upper surface of a negative electrode (5). The method includes the steps of: (i) laminating resist (16) on the negative electrode (5) and the positive electrode (6) and forming openings (16a and 16b) in the resist (16); (ii) forming bumps (11 and 12) in the respective openings (16a and 16b); (iii) removing the resist (16); and (iv) bonding bumps (11 and 12) to the ceramic substrate (9). A cross-sectional area of the opening (16a) is larger than a cross-sectional area of the opening (16b).Type: GrantFiled: June 8, 2011Date of Patent: June 2, 2015Assignee: Sharp Kabushiki KaishaInventors: Yasuhiro Koyama, Katsuji Kawakami, Mutsuo Kawasaki, Osamu Miyake, Hajime Oda, Keiichi Sawai
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Publication number: 20130065331Abstract: The present invention is a method for mounting, on a ceramic substrate (9), an LED chip (1), in which an upper surface of a positive electrode (6) is in a higher position than an upper surface of a negative electrode (5). The method includes the steps of: (i) laminating resist (16) on the negative electrode (5) and the positive electrode (6) and forming openings (16a and 16b) in the resist (16); (ii) forming bumps (11 and 12) in the respective openings (16a and 16b); (iii) removing the resist (16); and (iv) bonding bumps (11 and 12) to the ceramic substrate (9). A cross-sectional area of the opening (16a) is larger than a cross-sectional area of the opening (16b).Type: ApplicationFiled: June 8, 2011Publication date: March 14, 2013Applicant: Sharp Kabushiki KaishaInventors: Yasuhiro Koyama, Katsuji Kawakami, Mutsuo Kawasaki, Osamu Miyake, Hajime Oda, Keiichi Sawai
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Patent number: 7605057Abstract: A method of manufacturing a semiconductor device can suppress the generation of burrs when an array of integrated circuits to which a supporting member is bonded for assistance is separated into chips. The supporting member having thinned regions (or void regions which are openings in the supporting member) located correspondingly beneath the scribing lines extending between the integrated circuits is bonded by an adhesive to the back side of a semiconductor substrate on which integrated circuits are arrayed at the primary side. Then, a dicing tape is attached to the support member to secure the entire assembly, and the assembly of the integrated circuits, the semiconductor substrate, the adhesive, and the supporting member are cut along the scribing lines, and then the dicing tape is removed.Type: GrantFiled: July 5, 2007Date of Patent: October 20, 2009Assignee: Sharp Kabushiki KaishaInventors: Akio Shimoyama, Hajime Oda, Keiichi Sawai, Takayuki Taniguchi
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Publication number: 20090149014Abstract: At step S101, a TiW film is formed by a sputtering method so as to cover a surface protection film and pad electrodes formed on a surface of a semiconductor element. Subsequently, an Au film is formed on the TiW film. At step S103, Au bumps are formed on the Au film using the Au film as a plating electrode. At step S105, unnecessary parts of the Au film are removed. At step S106, unnecessary parts of the TiW film are removed. At step S107, iodine left in areas where the unnecessary parts of the TiW film have been removed, is removed.Type: ApplicationFiled: April 7, 2008Publication date: June 11, 2009Inventors: Norimitsu NIE, Masahiro HORIO, Keiichi SAWAI, Yuji WATANABE, Yasuhiro KOYAMA, Katsuji KAWAKAMI
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Publication number: 20090038957Abstract: In a stable gold plating liquid having a low toxicity besides properties comparable to those of a cyan-type gold plating liquid, iodine and/or iodide ions, gold ions, and a polyalcohol having at least 4 carbon atoms are contained. The polyalcohol having at least 4 carbon atoms may be diethylene glycol or triethylene glycol. The content of the polyalcohol having at least 4 carbon atoms in the gold plating liquid is generally 10 to 90 percent by weight. The gold plating liquid may contain water.Type: ApplicationFiled: October 21, 2005Publication date: February 12, 2009Applicants: MITSUBISHI CHEMICAL CORPORATION, SHARP KABUSHIKI KAISHAInventors: Toshiaki Sakakihara, Yasuhiro Kawase, Fumikazu Mizutanii, Makoto Ishikawa, Yoshihide Suzuki, Keiichi Sawai
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Patent number: 7473380Abstract: An etching liquid contains iodine, an iodine compound and alcohol as solute, and solvent such as water. The etching liquid etches a gold or gold alloy layer formed on the surface of a substrate for a semiconductor device or a liquid crystal device evenly. A plurality of gold or gold alloy columns is formed on the layer. The columns are etched scarcely by the etching liquid. The etching liquid etches the gold or gold alloy layer existing between the columns evenly. The etching liquid may further contain a surfactant.Type: GrantFiled: November 22, 2002Date of Patent: January 6, 2009Assignees: Sharp Kabushiki Kaisha, Mitsubishi Chemical CorporationInventors: Yoshihide Suzuki, Keiichi Sawai, Noriyuki Saitou, Masaru Miyoshi, Makoto Ishikawa
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Publication number: 20080032485Abstract: A method of manufacturing a semiconductor device can suppress the generation of burrs when an array of integrated circuits to which a supporting member is bonded for assistance is separated into chips. The supporting member having thinned regions (or void regions which are openings in the supporting member) located correspondingly beneath the scribing lines extending between the integrated circuits is bonded by an adhesive to the back side of a semiconductor substrate on which integrated circuits are arrayed at the primary side. Then, a dicing tape is attached to the support member to secure the entire assembly, and the assembly of the integrated circuits, the semiconductor substrate, the adhesive, and the supporting member are cut along the scribing lines, and then the dicing tape is removed.Type: ApplicationFiled: July 5, 2007Publication date: February 7, 2008Applicant: Sharp Kabushiki KaishaInventors: Akio Shimoyama, Hajime Oda, Keiichi Sawai, Takayuki Taniguchi
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Publication number: 20070145003Abstract: In a method of etching a semiconductor device or a liquid crystal device, an etching liquid is prepared to include a solvent, and a solute containing at least iodine, at least one iodine compound and alcohol. The etching liquid is applied to a substrate of the semiconductor device or the liquid crystal device having plural gold columns on a gold layer or gold alloy columns on a gold alloy layer.Type: ApplicationFiled: February 22, 2007Publication date: June 28, 2007Applicants: MITSUBISHI CHEMICAL CORPORATION, SHARP KABUSHIKI KAISHAInventors: Yoshihide Suzuki, Keiichi Sawai, Noriyuki Saitou, Masaru Miyoshi, Makoto Ishikawa
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Publication number: 20060118952Abstract: The present invention provides a micro-hole plating method for depositing a gold layer within a micro opening of a photoresist. The method applies a plating current, which is either only a positive pulse current or a positive/negative pulse current having an appropriate waveform, and also uses a gold plating solution containing gold iodide complex ions and a non-aqueous solvent. This plating solution is less toxic, not easily oxidized, and has a long life, thus offering great performance comparable with the cyanide-type gold plating solution. According to this method, unevenness of bump surface, bump height variation in the wafer, and the bump surface roughness are reduced, and the resulting gold bumps have highly reliable conduction. In addition to this, the method is immune to a short circuit among electrodes, which is caused by a crack in the resist.Type: ApplicationFiled: November 2, 2005Publication date: June 8, 2006Inventors: Yoshihide Suzuki, Keiichi Sawai
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Publication number: 20040209464Abstract: A shielding plate (7) having an opening section is inserted between a semiconductor substrate (substrate to be plated) (4) and an anode electrode (5). An outer edge of the opening section of the shielding plate (7) is smaller than an outer edge of the semiconductor substrate (4) by a predetermined distance. The predetermined distance is set so that a difference between a size of the semiconductor substrate (4) and a size of the opening section has an optimum value that enables a plating film (bump electrode) to have a uniform thickness on an entire surface of the semiconductor substrate (4). With this, it is possible to provide a plating method and plating device capable of forming a plating film having almost no variation in thickness by providing a shielding plate having a simple shape, without increasing the cost of the plating device.Type: ApplicationFiled: January 23, 2004Publication date: October 21, 2004Inventors: Keiichi Sawai, Osamu Miyake
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Publication number: 20040206622Abstract: A plating processing device is so arranged that at least a part of a portion touching plating liquid is made of a material whose change rate of surface roughness in response to a removing agent is lower than resin when the material and the resin are measured in the same conditions. For example, a storage tank (1), a plating processing tank (2), a buffer tank (3), and a pipe (9) are made of hard glass and quartz glass. With this, it is possible to prevent a plating material from being deposited as foreign body on wall surfaces of the plating processing tank, etc.Type: ApplicationFiled: January 23, 2004Publication date: October 21, 2004Inventors: Katsuji Kawakami, Keiichi Sawai, Hajime Oda
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Patent number: 6717263Abstract: In a semiconductor chip mounted in a semiconductor device, when an opening portion (2) is formed in a surface protective film (14) on a pad (13), the opening portion (2) is so formed as to have a plurality of openings (15), each smaller than a tip diameter of a probe needle (17) and arranged in a grid pattern or stripe pattern. In this configuration, electrical continuity is achieved between the probe needle (17) and the pad (13) through a bump electrode (16) if the bump electrode is properly formed. Electrical continuity between the probe needle (17) and the pad (13) is prevented by the opening (15) and is not achieved if the bump electrode (16) is improperly formed.Type: GrantFiled: October 29, 2002Date of Patent: April 6, 2004Assignee: Sharp Kabushiki KaishaInventors: Keiichi Sawai, Osamu Jinushi
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Publication number: 20030100191Abstract: An etching liquid contains iodine, an iodine compound and alcohol as solute, and solvent such as water. The etching liquid etches a gold or gold alloy layer formed on the surface of a substrate for a semiconductor device or a liquid crystal device evenly. A purality of gold or gold alloy columns are formed on the layer. The columns are etched scarcely by the etching liquid. The etching liquid etches the gold or gold alloy layer existing between the columns evenly. The etching liquid may further contain a surfactant.Type: ApplicationFiled: November 22, 2002Publication date: May 29, 2003Applicant: SHARP KABUSHIKI KAISHA and MITSUBISHI CHEMICAL CORPORATIONInventors: Yoshihide Suzuki, Keiichi Sawai, Noriyuki Saitou, Masaru Miyoshi, Makoto Ishikawa
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Publication number: 20030080421Abstract: In a semiconductor chip mounted in a semiconductor device, when an opening portion (2) is formed in a surface protective film (14) on a pad (13), the opening portion (2) is so formed as to have a plurality of openings (15), each smaller than a tip diameter of a probe needle (17) and arranged in a grid patter or stripe pattern. In this configuration, electrical continuity is achieved between the probe needle (17) and the pad (13) through a bump electrode (16) if the bump electrode is properly formed. Electrical continuity between the probe needle (17) and the pad (13) is prevented by the opening (15) and is not achieved if the bump electrode (16) is improperly formed.Type: ApplicationFiled: October 29, 2002Publication date: May 1, 2003Inventors: Keiichi Sawai, Osamu Jinushi