Patents by Inventor Keiichi Takenaka

Keiichi Takenaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180076266
    Abstract: A semiconductor device according to the embodiment includes a plurality of semiconductor layers arranged along a first direction and a second direction, wherein each of the semiconductor layers includes a first semiconductor layer and second semiconductor layers positioned at both upper and lower sides of the first semiconductor layer, and a gate electrode which faces the first semiconductor layer. A row of the semiconductor layer in the first direction is oblique to a row of the semiconductor layer in the second direction. At least one part of peripheral faces of the first semiconductor layer is in contact with the gate electrode along the first direction.
    Type: Application
    Filed: February 2, 2017
    Publication date: March 15, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Yusuke GOKI, Keiichi TAKENAKA
  • Patent number: 9917138
    Abstract: A semiconductor device according to the embodiment includes a plurality of semiconductor layers arranged along a first direction and a second direction, wherein each of the semiconductor layers includes a first semiconductor layer and second semiconductor layers positioned at both upper and lower sides of the first semiconductor layer, and a gate electrode which faces the first semiconductor layer. A row of the semiconductor layer in the first direction is oblique to a row of the semiconductor layer in the second direction. At least one part of peripheral faces of the first semiconductor layer is in contact with the gate electrode along the first direction.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: March 13, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yusuke Goki, Keiichi Takenaka
  • Patent number: 7387921
    Abstract: Disclosed is a method of manufacturing a semiconductor device, comprising forming a gate electrode on a main surface of a semiconductor substrate via a gate insulating film, laminating sequentially a first insulating film with oxidation resistance and a silicon film on the main surface of the semiconductor substrate on which the gate electrode is formed, eliminating selectively the silicon film except for a side face of the gate electrode, and oxidizing the silicon film to transform it into a first silicon oxide film, eliminating the first insulating film on the main surface of the semiconductor substrate by using the first silicon oxide film as a mask, and then forming a first impurity layer on the main surface of the semiconductor substrate, laminating a sidewall insulating film thicker than the first silicon oxide film on the side face of the gate electrode on which the first silicon oxide film is formed, and forming a second impurity layer which has the same conduction type as that of the first impurity l
    Type: Grant
    Filed: November 23, 2005
    Date of Patent: June 17, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsunori Yahashi, Keiichi Takenaka
  • Publication number: 20060231877
    Abstract: A semiconductor device comprises a semiconductor substrate having a surface of a plane orientation {100}, and a plurality of memory cells formed on the semiconductor substrate. The memory cells each include a capacitor formed in a trench extending from the surface into the semiconductor substrate, and a transistor. The transistor has a first source/drain region connected to the capacitor, a second source/drain region formed apart from the first source/drain region as leaving an interval therebetween and connected to a bit line, and a gate electrode formed over the interval between the first and second source/drain regions and connected to a word line. A transverse section of at least part of the trench is tetragonal. Transverse sections of the trenches in the memory cells are tilted at the substantially same angle against a direction of extension of the word line.
    Type: Application
    Filed: June 17, 2005
    Publication date: October 19, 2006
    Inventors: Keiichi Takenaka, Katsunori Yahashi, Itsuko Sakai
  • Publication number: 20060138413
    Abstract: Disclosed is a method of manufacturing a semiconductor device, comprising forming a gate electrode on a main surface of a semiconductor substrate via a gate insulating film, laminating sequentially a first insulating film with oxidation resistance and a silicon film on the main surface of the semiconductor substrate on which the gate electrode is formed, eliminating selectively the silicon film except for a side face of the gate electrode, and oxidizing the silicon film to transform it into a first silicon oxide film, eliminating the first insulating film on the main surface of the semiconductor substrate by using the first silicon oxide film as a mask, and then forming a first impurity layer on the main surface of the semiconductor substrate, laminating a sidewall insulating film thicker than the first silicon oxide film on the side face of the gate electrode on which the first silicon oxide film is formed, and forming a second impurity layer which has the same conduction type as that of the first impurity l
    Type: Application
    Filed: November 23, 2005
    Publication date: June 29, 2006
    Inventors: Katsunori Yahashi, Keiichi Takenaka
  • Publication number: 20060137988
    Abstract: According to an aspect of the present invention, a semiconductor manufacturing apparatus, including: a treatment chamber configured to house a substrate; an electrode which is disposed in said treatment chamber and on which the substrate is placed; a robot arm configured to convey the substrate to said electrode; and a sensor configured to detect a detection pattern of a focus ring which is disposed on an outer peripheral edge portion of said electrode, surrounds an peripheral edge of the substrate placed on said electrode and has the detection pattern, wherein clearance between the substrate and the focus ring is adjusted based on detection result of said sensor, is provided.
    Type: Application
    Filed: March 16, 2005
    Publication date: June 29, 2006
    Inventors: Katsunori Yahashi, Keiichi Takenaka, Masaki Narita, Itsuko Sakai
  • Publication number: 20060128093
    Abstract: A method of manufacturing a semiconductor device is provided. The method comprises forming a mask member on a surface of a semiconductor substrate; and forming a trench in the semiconductor substrate by selectively etching the semiconductor substrate with a mask of the mask member under a certain pressure. The pressure is changed on arrival of (Etching Depth)/(Aperture Width in said surface) at 30 or more for the remainder of the etching by a factor ranging from 1/2 to 9/10 relative to the pressure at the time of the arrival.
    Type: Application
    Filed: April 14, 2005
    Publication date: June 15, 2006
    Inventors: Keiichi Takenaka, Katsunori Yahashi, Itsuko Sakai, Masaki Narita
  • Publication number: 20040188739
    Abstract: A semiconductor device includes a semiconductor substrate, a trench including a narrowed portion and a main part, a diameter of the narrowed portion being coaxially smaller than a diameter of the trench at the main part, a first capacitor electrode provided in the semiconductor substrate so as to surround the trench inclusive of the narrowed portion, a capacitor insulating film provided along a surface of the first capacitor electrode, a second capacitor electrode provided inside the trench.
    Type: Application
    Filed: January 8, 2004
    Publication date: September 30, 2004
    Inventors: Keiichi Takenaka, Itsuko Sakai, Masaki Narita, Tokuhisa Ohiwa, Atsuo Sanda, Katsunori Yahashi