Abstract: An information processing apparatus includes: a selection unit for analyzing attribute information units, which are added upon shooting to at least one still image to be played back, and selecting a predetermined attribute information unit to be displayed together with the still image; and a playback unit for playing back a music track selected by a user, applying at least one effect related to the music track selected by the user, and displaying the still image and text indicating the selected predetermined attribute information unit with the effect on the same screen.

Abstract: A program-display control apparatus can display information on each of a plurality of programs in a state that can be recognized by the user with ease without regard to the display configuration of the display data of the program. A display-configuration modification unit changes the display configurations of the program table of a BS digital broadcast, the program table of a ground wave broadcast, and a WEB program table into a new display configuration which increases the amount of information on the programs without regard to the display configuration of each of the programs. Furthermore, a program-table creation unit creates display data according to the new display configuration and outputs the display data.

Abstract: A semiconductor device layout method is disclosed, wherein vias carrying the same signal are arranged at intervals equal to the minimum value defined by a design rule, and vias carrying different signals are arranged at second intervals that are greater than the minimum value.

Abstract: The present invention enables a user to retrieve his or her desired one of a number of image programs easily and to view it quickly.

Abstract: A parallel processor and an image processing system incorporating such processor are disclosed. Control signals in the parallel processor are generated by an instruction sequence control unit, and divided into two: global control signals supplied to a local signal generator of arbitrary selected processor element group; and local control signals buffered by the local control signal generator and then supplied exclusively to the processor elements included in arbitrary selected processor element group. This construction of the processor alleviates deterioration in device characteristics and undesirable increase in driving power requirements.

Abstract: A semiconductor integrated circuit device and a fabrication method thereof are disclosed, for effective suppression of a temperature increase therein that is caused by heat generation of a semiconductor element. The semiconductor integrated circuit device includes a semiconductor element, a multi-layer wiring structure and a heat conduction part. The semiconductor element is formed on a support substrate. The multi-layer wiring structure is formed in an insulation film on the support substrate and includes at least one connection hole and at least one metal wiring layer. The heat conduction part is formed of the same conductive materials as the connection hole and the metal wiring layer and extends toward an upper layer side along a path different from a wiring path including a connection hole and a metal wiring for signal transmission.

Abstract: A semiconductor integrated circuit device fabricated with reduced size and wiring to alleviate wiring delay, and an improved placement and routing method of the building-block type for appropriate use in deep-submicron processes for fabricating such semiconductor device. This semiconductor integrated circuit device includes at least a plurality of integrated circuit blocks to be interconnected by wiring, and a terminal cell including a terminal target metal that is different from, and formed in a layer higher at least by one layer than, ordinary target metals originally included in a block netlist. The interconnection among the integrated circuit blocks is carried out by way of the block terminals provided in circumferential edge portions on the block layout and the terminal target of the terminal cell.

Abstract: In a personal broadcasting system, a user terminal vertically divides a window serving as a main screen into separate elements corresponding to a plurality of functions on a display screen and causes a display unit to display the separate elements side-by-side, the separate elements being a plurality of independent panel windows.

Abstract: The present invention is capable of easily and quickly selecting and applying desired effects. In the present invention, single-shot effects and continuous effects for specifying special effects for images are arranged and displayed in the order of use in a single-effect display area 105A and a continuous effect display area 105B of an effect list display area 105, so that the user can easily and quickly select a single-shot effect and a continuous effect to apply desired special effects, in order to easily and quickly apply the desired special effects to input image at desired timing.

Abstract: A semiconductor integrated circuit device fabricated with reduced size and wiring to alleviate wiring delay, and an improved placement and routing method of the building-block type for appropriate use in deep-submicron processes for fabricating such semiconductor device. This semiconductor integrated circuit device includes at least a plurality of integrated circuit blocks to be interconnected by wiring, and a terminal cell including a terminal target metal that is different from, and formed in a layer higher at least by one layer than, ordinary target metals originally included in a block netlist. The interconnection among the integrated circuit blocks is carried out by way of the block terminals provided in circumferential edge portions on the block layout and the terminal target of the terminal cell.

Abstract: A parallel processor and an image processing system incorporating such processor are disclosed. Control signals in the parallel processor are generated by an instruction sequence control unit, and divided into two: global control signals supplied to a local signal generator of arbitrary selected processor element group; and local control signals buffered by the local control signal generator and then supplied exclusively to the processor elements included in arbitrary selected processor element group. This construction of the processor alleviates deterioration in device characteristics and undesirable increase in driving power requirements.

Abstract: When data that does not fill a bit size (32 bits) of a first register is stored in the first register, 8-bit data is supplied from a second register or a first constant generator to unfilled higher 16 bit positions of the first register, and a second constant generator supplies 8-bit data to fill the remaining bit positions in the first register.

Abstract: A general-use register set includes a plurality of registers in a central processing unit body. A register-bank memory has memory regions relevant to the plurality of registers and is connected to the central processing unit. An output signal of an address circuit included in the central processing unit is supplied to the register-bank memory. Alternatively, an output signal of a decoding circuit included in the central processing unit may be supplied to the register-bank memory. A signal for selecting either activation or deactivation of the register-bank memory is a signal which indicates a selection of the deactivation of the register-bank memory except in a case where data is written in the general-use register set and a case of a restoration operation after register bank switching.

Abstract: A microprocessor having an instruction prefetch function includes a storage circuit in which an instruction externally supplied to the microprocessor via an external interface is stored, a first latch circuit which latches a write address value of the storage circuit in response to an interrupt signal externally supplied to the microprocessor, and an internal interrupt signal outputting circuit which compares a read address value of the storage circuit indicating the instruction stored in the storage circuit with the write address value supplied from the first latch circuit and which generates the internal interrupt signal only when the read address value and the write address value coincide with each other. The microprocessor processes an interrupt process in response to the internal interrupt signal.

Abstract: A general-use register set includes a plurality of registers in a central processing unit body. A register-bank memory has memory regions relevant to the plurality of registers and is connected to the central processing unit. An output signal of an address circuit included in the central processing unit is supplied to the register-bank memory. Alternatively, an output signal of a decoding circuit included in the central processing unit may be supplied to the register-bank memory. A signal for selecting either activation or deactivation of the register-bank memory is a signal which indicates a selection of the deactivation of the register-bank memory except in a case where data is written in the general-use register set and a case of a restoration operation after register bank switching.

Abstract: An integrated circuit has a central processing unit for executing programs. The integrated circuit includes a register set, provided in the central processing unit, for storing crate required for executing a program in the central processing unit; and a register-file RAM, coupled to the central processing unit, for storing at least the same data as that stored in the register set in the central processing unit, wherein data stored in the register-file RAM can be supplied to the register set in the central processing unit.

Abstract: A central processing unit includes an instruction register storing instruction codes, a timing control unit controlling timings of steps of execution of an instruction, an execution unit executing an operation on data and temporarily storing data, the execution unit having a program counter and a data bus, a decoder decoding instruction codes read from the instruction register and controlling the instruction register, the timing control unit and the execution unit, and a next enable unit receiving an indication signal indicating proceeding to a next instruction should be performed and controlling outputting of the indication signal to the instruction register and the timing control unit based on first and second signals. The first signal is supplied from the decoder and instructing data on the data bus to be input to the program counter. The second signal is supplied from the execution unit and indicating whether a counter value of the program counter is an odd number or an even number.

Abstract: A general-purpose register group circuit provided in a data processing system includes a plurality of register groups connected to a first bus and a second bus, data being written into the plurality of register groups via the first bus according to a first control signal and being read therefrom via the second bus according to a second control signal. An output register group is connected to the plurality of register groups via the first and second buses. The data read from the plurality of register groups is written into the output register group according to a third control signal, and data read from the output register group is sent to an inner bus of the data processing system according to a fourth control signal. Each of the plurality of register groups includes a plurality of unit registers, each of which registers includes a first part for setting the second bus to either a high-impedance state or a reference level according to data latched therein and the second control signal.