Abstract: When a trigger clock is input, its leading and trailing edges are detected, and first and second oscillators are started to oscillate by the leading and trailing edge detected outputs, respectively. The first and second oscillators oscillate at the same oscillation frequency, which is determined by data set in period setting means. A flip-flop is set by the output of the first oscillator and reset by the output of the second oscillator and the flip-flop output is provided as multi-clock pulses. The number of multi-clock pulses from the flip-flop is counted by a clock counter, and when it is detected by a stop detector that the clock counter has counted to a preset value, the first and second oscillators are stopped, by the detected output, from oscillation.