Abstract: A communication network and its user i has a device for implementing a common key cryptosystem, an identifier of the user i represented by ID.sub.i which is made public in the network, an authentication key of a user i represented by S.sub.i is known only to the network and the user i and these identifiers and authentication keys of all the users are stored in a database of the network. Data for authentication and encrypted data of a cipher key for the subsequent privacy communication are sent from the network to the user, the user presents his identifier (ID) to the network, after which up to three interactions take place between the network and the user to perform the required authentications and distribution of the cipher key.

Abstract: A sequential decoding of a convolutionally encoded sequence has been proposed. Decoding is carried out by extending paths along the branches of code-tree over plural tree levels at a time and calculating likelihood (metric) of the extended paths referring to the received sequence. Decoding is terminated when it proceeds to a node belonging to the last tree level of a data block. Then, one of the extended sequences associated with a node located at the last tree level which has the largest metric is output as a decoded sequence.

Abstract: A satellite communication among a plurality of small earth stations (very small aperture terminal;VSAT) through a satellite is performed by using a relay earth station which has higher power than a small earth station. A signal goes from an originating small earth station to a destination small earth station, through a satellite, a relay earth station, and a satellite by using two hops propagation. Communication is carried out in digital form. The relay earth station regenerates digital signals from small earth stations. In the process of the regeneration of the digital signals, the error correction technique is applied to reduce the error rate, and a frequency compensation technique is also employed. Thus, a small simple earth station can provide high quality of communication with high C/N. A reference clock signal for operating a small earth station is derived from a reception signal from a satellite.

Abstract: In an error correction code decoding system using BCH (Bose-Chaudhuri-Hocquenghem) code for correcting error bits in input data Y=(y.sub.1, y.sub.2, - - - , y.sub.n) having the steps of obtaining syndrome S=(S.sub.1, S.sub.2, - - , S.sub.n) through calculation of YH.sup.t, where H is a parity check matrix, obtaining determinant Q.sub.t (equation 6) which has elements of said syndrome S=(S.sub.1, S.sub.2, - - - , S.sub.n), and Q determinant which is provided by deleting some rows and columns including specified diagonal elements of said Q.sub.

Abstract: An improved two or three error correcting system for BCH code (Bose, Chaudhuri, Hocquenghem code) has been found. In case of a two error correction system, a first syndrome A.sub.1 and a second syndrome A.sub.2 are obtained from a reception code C'=(a.sub.1 ', a.sub.2 ', . . . , a.sub.n '): ##EQU1## Then, S.sub.1 =A.sub.1 +.alpha..sup.n-t, and S.sub.2 =A.sub.2 +.alpha..sup.3(n-t) are obtained, for every value of t, where n is a code length, t is an integer equal to or less than n, and .alpha. is a primitive element of a Galois field. When A.sub.1 .noteq.0, a t'th bit a.sub.t ' is corrected by inverting the same on the condition that the t'th bit of S.sub.2 is equal to the t'th bit of S.sub.1.sup.3. When A.sub.1 =0, it is clear that no error exists, and no correction is performed. In case of a three error correction system, a third syndrome ##EQU2## and S.sub.3 =A.sub.3 +.alpha..sup.

Abstract: An electronic timepiece having voltage regulation, temperature detection and battery voltage detection means provided on the same integrated circuit as is used for timekeeping circuitry, and having external terminals for stepwise weighted adjustment of timekeeping gain/loss.

Abstract: The invention converts between a cyclic and a general code sequence, each sequence having a succession of normal code blocks and an additional or shorter code block. A zero bit series is hypothetically assumed before the additional code block. In an encoder for producing a cyclic code sequence, the zero bit series is placed before the additional code block by cooperation of a timing control circuit and a divider. In a decoder, a counter times an additional cyclic code block and starts counting while another counter is still counting to time a period, which is the period next preceding a normal cyclic code block, whereby the zero bit series is assumed.

Abstract: An electronic timepiece includes a primary timepiece circuit unit including a frequency supply for providing a relatively high frequency signal, a frequency converter responsive to the relatively high frequency signal to provide a relatively low frequency time unit signal, timing signals, and a plurality of word pulses indicative of a plurality of data words representing time data concerning the current time, and a set of additional data other than the time data, a timekeeping register arranged to store the time data and the additional data, and display elements for displaying the time data and the additional data. A secondary timepiece circuit unit includes a register arranged to store the additional data to be transferred to the timekeeping register.

Abstract: An electronic timepiece includes a frequency supply for providing a relatively high frequency time base signal, a circuit including a frequency converter responsive to the time base signal to provide a relatively low frequency time unit signal, and a time-keeping register responsive to the time unit signal to produce a time information signal. An input means includes an external control to provide an actuation signal when actuated, and an input signal is generated in response to the actuation signal, provision being made for selectively rendering the input signal generating means inoperative. An enabling signal is generated in response to the input signal and the time information signal, and a control responsive to the enabling signal controls the circuit means to correct the time information signal.

Abstract: An electronic timepiece having voltage regulation, temperature detection and battery voltage detection means provided on the same integrated circuit as is used for timekeeping circuitry, and having external terminals for stepwise weighted adjustment of timekeeping gain/loss.

Abstract: An electronic timepiece includes a frequency supply for providing a relatively high frequency time base signal, a frequency converter responsive to the time base signal to provide a relatively low frequency time unit signal, and timekeeping means responsive to the time unit signal to provide current time information. The current time information is corrected and displayed. A calculation command signal is generated and enables a circuit means to produce, in response to the time unit signal, a frequency error signal indicative of an error in the frequency of the time unit signal. A gain/loss adjustment signal is generated in response to the frequency error signal, and a frequency adjusting circuit is provided for adjusting the frequency of the time unit signal in response to the gain/loss adjustment signal.

Abstract: An electronic timepiece includes a frequency supply for providing a relatively high frequency time base signal, a frequency converter responsive to the time base signal to provide a relatively low frequency time unit signal, timing signals, and a plurality of word pulses indicative of a plurality of data words representing time data concerning the current time and additional data concerning alarm time. A timekeeping register stores the time data and the additional data and provision is made for generating a carry signal in dependence on the time data. The information in the register is altered in response to the time unit signal and the carry signal to update the time data and provision is made to write in the additional data into the register. The coincidence between the current time and the alarm time is detected by an alarm unit which generates a coincidence signal indicative thereof.

Abstract: An electronic timepiece includes a frequency supply for providing a relatively high frequency time base signal, a frequency converter responsive to the time base signal to provide a relatively low frequency time unit signal, timing signals, and a plurality of word pulses indicative of plurality of data words representing time data concerning the current time, and a set of additional data other than the time data. A primary register is arranged to store the time data and the additional data, and display means displays the time data and the additional data. An external control member is adapted to provide an input signal when actuated, and an indexing signal is generated in response to the input signal.

Abstract: An electronic timepiece includes a frequency supply for providing a relatively high frequency time base signal, a frequency converter responsive to the relatively high frequency time base signal to provide a timing signal, a clock signal, and a time unit signal. A timekeeping circuit is responsive to the time unit signal to provide a time information signal, and at least one of the timing signal, clock signal, and time information signal is chopped into periodic bursts to effect transfer of the at least one of the timing signal, clock signal, and time information signal from one part to another part in the timepiece. The time in response to the time information signal is displayed.