Abstract: According to an embodiment, a capacitor includes a conductive substrate, a conductive layer, and a dielectric layer. The conductive substrate has a first main surface and a second main surface and is provided with a plurality of recesses on the first main surface. The conductive substrate is further provided with a plurality of holes in one or more portions each sandwiched between two adjacent ones of the recesses such that a region on a side of the first main surface has a larger porosity than a region on a side of the second main surface. The conductive layer covers the first main surface, side walls and bottom surfaces of the recesses, and walls of the holes. The dielectric layer is interposed between the conductive substrate and the conductive layer.

Abstract: A semiconductor device includes a substrate; a semiconductor chip located on the substrate; a sealing resin covering the substrate and the semiconductor chip; and a mottled pattern located at an interface between the sealing resin and at least one of the substrate or the semiconductor chip.

Abstract: According to one embodiment, a capacitor includes a conductive substrate, a conductive layer, a dielectric layer, and first and second external electrodes. The conductive substrate has a first main surface provided with recess(s), a second main surface, and an end face extending between edges of the first and second main surfaces. The conductive layer covers the first main surface and side walls and bottom surfaces of the recess(s). The dielectric layer is interposed between the conductive substrate and the conductive layer. The first external electrode includes a first electrode portion facing the end face and is electrically connected to the conductive layer. The second external electrode includes a second electrode portion facing the end face and is electrically connected to the conductive substrate.

Abstract: A capacitor according to an embodiment includes a substrate having a first surface and a second surface and provided with one or more first through holes each extending from the first surface to the second surface, a first conductive layer covering the first surface, the second surface, and side walls of the one or more first through holes, a second conductive layer facing the first surface, the second surface, and the side walls of the one or more first through holes, with the first conductive layer interposed therebetween, and a dielectric layer interposed between the first conductive layer and the second conductive layer.

Abstract: A power module includes a base plate, a casing, a substrate unit, a terminal plate, a first resin layer, and a second resin layer. The substrate unit includes a substrate fixed on the base plate, a dam part, a semiconductor chip, a metal member, and a wire. The dam part is formed along an edge of the substrate. The wire includes an electrode plate connection portion, and a chip connection portion. The first resin layer is located inward of the dam part. The chip connection portion and the electrode plate connection portion are located inside the first resin layer. The second resin layer is located on the first resin layer. The upper surface of the metal member is located inside the second resin layer. An elastic modulus of the second resin layer is less than that of the first resin layer.

Abstract: A power module includes: a base plate having a first surface; electrode plate provided at the first surface; a wire connected to a semiconductor chip and the electrode plate; a metal member connected to the electrode plate; a terminal plate; a first resin layer, a connection portion of the wire and the semiconductor chip being disposed inside the first resin layer; and a second resin layer provided on the first resin layer and having a lower elastic modulus than the first resin layer. The terminal plate includes a bonding portion contacting an upper surface of the metal member, a curved portion curved upward from the bonding portion. The curved portion is disposed inside the second resin layer, and a length from the first surface of a lower surface of the bonding portion is greater than a length from the first surface of the connection portion.

Abstract: A semiconductor wafer includes a surface having at least one recess including an inner wall surface. The inner wall surface is exposed.

Abstract: According to an embodiment, a method of forming a catalyst layer includes performing displacement plating on a substrate having a surface that is made of a semiconductor and includes a plurality of projections, thereby depositing a catalytic metal at positions of the plurality of projections.

Abstract: According to an embodiment, a method of forming a porous layer includes forming a porous layer containing a noble metal on a surface made of a semiconductor by displacement plating. The plating solution used in the displacement plating contains a noble metal source, hydrogen fluoride, and an adjusting agent adjusting a pH value or zeta potential. The noble metal source produces an ion containing the noble metal in water. The plating solution has a pH value in a range of 1 to 6.

Abstract: According to one embodiment, a capacitor includes a conductive substrate, a conductive layer, a dielectric layer, and first and second external electrodes. The conductive substrate has a first main surface provided with recess(s), a second main surface, and an end face extending between edges of the first and second main surfaces. The conductive layer covers the first main surface and side walls and bottom surfaces of the recess(s). The dielectric layer is interposed between the conductive substrate and the conductive layer. The first external electrode includes a first electrode portion facing the end face and is electrically connected to the conductive layer. The second external electrode includes a second electrode portion facing the end face and is electrically connected to the conductive substrate.

Abstract: According to an embodiment, a method of forming a porous layer includes forming a porous layer containing a noble metal on a surface made of a semiconductor by displacement plating. The plating solution used in the displacement plating contains a noble metal source, hydrogen fluoride, and an adjusting agent adjusting a pH value or zeta potential. The noble metal source produces an ion containing the noble metal in water. The plating solution has a pH value in a range of 1 to 6.

Abstract: According to one embodiment, in a processing system and determining method, a X-ray intensity of character X-rays generated by irradiating a catalytic layer of a noble metal formed on a surface of a substrate with X-rays is detected. In the processing system and the determining method, either the detected X-ray intensity or a parameter calculated using the X-ray intensity is obtained as a determination parameter. In the processing system and the determining method, based at least on the determination parameter, whether or not the catalytic layer has been formed into a state suitable for etching the surface of the substrate is determined.

Abstract: According to one embodiment, a capacitor includes a conductive substrate, a conductive layer, a dielectric layer, and first and second external electrodes. The conductive substrate has a first main surface provided with recess(s), a second main surface, and an end face extending between edges of the first and second main surfaces. The conductive layer covers the first main surface and side walls and bottom surfaces of the recess(s). The dielectric layer is interposed between the conductive substrate and the conductive layer. The first external electrode includes a first electrode portion facing the end face and is electrically connected to the conductive layer. The second external electrode includes a second electrode portion facing the end face and is electrically connected to the conductive substrate.

Abstract: A power module includes: a base plate having a first surface; electrode plate provided at the first surface; a wire connected to a semiconductor chip and the electrode plate; a metal member connected to the electrode plate; a terminal plate; a first resin layer, a connection portion of the wire and the semiconductor chip being disposed inside the first resin layer; and a second resin layer provided on the first resin layer and having a lower elastic modulus than the first resin layer. The terminal plate includes a bonding portion contacting an upper surface of the metal member, a curved portion curved upward from the bonding portion. The curved portion is disposed inside the second resin layer, and a length from the first surface of a lower surface of the bonding portion is greater than a length from the first surface of the connection portion.

Abstract: An etching method according to an embodiment includes forming an uneven structure including a projection on a surface of a semiconductor substrate; forming a catalyst layer including a noble metal on the surface selectively at a top surface of the projection; and supplying an etchant to the catalyst layer to cause an etching of the semiconductor substrate with an assist from the noble metal as a catalyst.

Abstract: A power transmission belt is at least partially formed of a rubber composition. The rubber composition contains a rubber component, cellulose nanofibers, and carbon black. The amount of the cellulose nanofibers to be added is from 0.1 parts by mass to 20 parts by mass, relative to 100 parts by mass of the rubber component. The amount of the carbon black to be added is from 5 parts by mass to 80 parts by mass, relative to 100 parts by mass of the rubber component. The sum of the amount of the carbon black to be added and three times the amount of the cellulose nanofibers to be added is from 15 to 90.

Abstract: A power transmission belt at least includes a bottom rubber layer. A rubber composition for forming the bottom rubber layer contains a rubber component, cellulose fine fibers, and short fibers. The cellulose fine fibers have an average diameter from 1 nm to 200 nm, and the rubber composition contains 0.5 parts by mass or more of the cellulose fine fibers relative to 100 parts by mass of the rubber component. The short fibers have an average diameter from 5 ?m to 30 ?m, and the rubber composition contains 1 part by mass or more of the short fibers relative to 100 parts by mass the rubber component.

Abstract: According to one embodiment, a capacitor includes a conductive substrate, a conductive layer, a dielectric layer, and first and second external electrodes. The conductive substrate has a first main surface provided with recess(s), a second main surface, and an end face extending between edges of the first and second main surfaces. The conductive layer covers the first main surface and side walls and bottom surfaces of the recess(s). The dielectric layer is interposed between the conductive substrate and the conductive layer. The first external electrode includes a first electrode portion facing the end face and is electrically connected to the conductive layer. The second external electrode includes a second electrode portion facing the end face and is electrically connected to the conductive substrate.

Abstract: According to an embodiment, a capacitor includes a conductive substrate, a conductive layer, and a dielectric layer. The conductive substrate has a first main surface and a second main surface and is provided with a plurality of recesses on the first main surface. The conductive substrate is further provided with a plurality of holes in one or more portions each sandwiched between two adjacent ones of the recesses such that a region on a side of the first main surface has a larger porosity than a region on a side of the second main surface. The conductive layer covers the first main surface, side walls and bottom surfaces of the recesses, and walls of the holes. The dielectric layer is interposed between the conductive substrate and the conductive layer.

Abstract: A capacitor according to an embodiment includes a substrate having a first surface and a second surface and provided with one or more first through holes each extending from the first surface to the second surface, a first conductive layer covering the first surface, the second surface, and side walls of the one or more first through holes, a second conductive layer facing the first surface, the second surface, and the side walls of the one or more first through holes, with the first conductive layer interposed therebetween, and a dielectric layer interposed between the first conductive layer and the second conductive layer.