Abstract: A nonvolatile semiconductor memory comprises a cell bias circuit supplying a first voltage, a memory cell array having memory cell transistors, word lines, drain lines disposed perpendicular to the word lines and source lines disposed perpendicular to the word lines.

Abstract: A nonvolatile semiconductor memory comprises a cell bias circuit supplying a first voltage, a memory cell array having memory cell transistors, word lines, drain lines disposed perpendicular to the word lines and source lines disposed perpendicular to the word lines.

Abstract: A non-volatile semiconductor memory decreases a parasitic current as much as possible without using an electric separation means. This nonvolatile semiconductor storage apparatus has multiple memory cells rows having multiple memory cell transistors M1, M2 . . . whose gates are connected to word lines WL1, WL2 . . . , respectively, and whose sources and drains are serially connected. This non-volatile semiconductor storage apparatus also has multiple column lines SBL0, SVL0, SVL1, SBL1 . . . which connect the connection nodes between the sources and drains of the memory cell transistors M1, M2 . . .

Abstract: A synchronous semiconductor burst nonvolatile semiconductor memory includes first and second address counter circuits and a counter selection circuit in order to output an address signal to a first latch circuit for storing therein data from a memory cell. Either the first address counter circuit or the second address counter circuit is alternately selected by the counter selection circuit in response to a burst control signal. According to the invention, either the first address counter circuit or the second address counter circuit is always selected, and a burst address signal is outputted to the latch circuit on the basis of an externally supplied address signal (first signal of the burst address signal) before the burst control signal is generated.