Patents by Inventor Keiichiro Tounai

Keiichiro Tounai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7974457
    Abstract: A method of testing a mask pattern, includes applying optical proximity-effect compensation to a first pattern to be tested and to be formed onto a mask layer, to thereby form a mask pattern of the mask layer, dividing the first pattern into a plurality of areas in accordance with a second pattern to be formed onto another mask layer, determining sampling points on an edge of the first pattern, determining a test standard for each of the areas, simulating a resist pattern formed on a resist by exposing the resist to a light through the mask pattern, and checking whether a dimensional gap between the first pattern and the resist pattern at each of the sampling points is within a test standard associated with an area to which each of the sampling points belongs, wherein test standards for first and second areas among the areas are different from each other.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: July 5, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Keiichiro Tounai
  • Patent number: 7058923
    Abstract: An optical proximity effect correcting method in a semiconductor manufacturing process includes adding, detecting, judging, and deleting. The adding includes adding a first correcting region around a portion of a first design pattern. The portion faces a second design pattern. A first corrected design pattern includes the first correcting region and the first design pattern. The detecting includes detecting a space between the first corrected design pattern and the second design pattern. The judging includes judging whether the space is smaller than or equal to a predetermined value. The deleting includes deleting at least a portion of the first correcting region such that the space is larger than the predetermined value, when the space is smaller than or equal to the predetermined value.
    Type: Grant
    Filed: December 4, 2001
    Date of Patent: June 6, 2006
    Assignee: NEC Electronics Corporation
    Inventors: Keiichiro Tounai, Takeshi Hamamoto
  • Publication number: 20040191648
    Abstract: A method of testing a mask pattern, includes applying optical proximity-effect compensation to a first pattern to be tested and to be formed onto a mask layer, to thereby form a mask pattern of the mask layer, dividing the first pattern into a plurality of areas in accordance with a second pattern to be formed onto another mask layer, determining sampling points on an edge of the first pattern, determining a test standard for each of the areas, simulating a resist pattern formed on a resist by exposing the resist to a light through the mask pattern, and checking whether a dimensional gap between the first pattern and the resist pattern at each of the sampling points is within a test standard associated with an area to which each of the sampling points belongs, wherein test standards for first and second areas among the areas are different from each other.
    Type: Application
    Filed: March 31, 2004
    Publication date: September 30, 2004
    Applicant: NEC Electronics Corporation
    Inventor: Keiichiro Tounai
  • Patent number: 6570174
    Abstract: An optical proximity effect correcting method in a semiconductor manufacturing process includes adding, detecting, judging, and deleting. The adding includes adding a first correcting region around a portion of a first design pattern. The portion faces a second design pattern. A first corrected design pattern includes the first correcting region and the first design pattern. The detecting includes detecting a space between the first corrected design pattern and the second design pattern. The judging includes judging whether the space is smaller than or equal to a predetermined value. The deleting includes deleting at least a portion of the first correcting region such that the space is larger than the predetermined value, when the space is smaller than or equal to the predetermined value.
    Type: Grant
    Filed: December 10, 1999
    Date of Patent: May 27, 2003
    Assignee: NEC Electronics Corporation
    Inventors: Keiichiro Tounai, Takeshi Hamamoto
  • Patent number: 6519759
    Abstract: To provide a photomask pattern shape correction method for suitably modifying and correcting a pattern deformation caused by a optical proximity effect. A corner 1 is extracted where an exterior angle of a wiring layer pattern is an angle of 90 degrees, which is out of a diffusion layer and where the distance R from the gate is within the predetermined value Rm and the interval between the gates is equal to or more than a set value Pm. A correction figure (A)11 is added to a side in the gate direction of this corner 1 and a correction figure (B)12 to the side not in the gate direction, and the interval G1 between the correction figure (B)12 and an adjacent correction figure is calculated, and the interval G1 calculated is checked whether it is equal to or more than the set value G1m.
    Type: Grant
    Filed: April 19, 2001
    Date of Patent: February 11, 2003
    Assignee: NEC Corporation
    Inventor: Keiichiro Tounai
  • Patent number: 6403477
    Abstract: A method for correcting an optical proximity effect in an exposure process includes the step of extracting corner portions of a mask interconnect pattern, providing a default “L”-shaped cutout correction pattern on the inner corner of the extracted corner portion, extracting a “]”-shaped pattern including a pair of corner portions in proximity, adjusting the distance of the opposing ends of the default cutout correction patterns in the “]”-shaped pattern to have a specified space. The method prevents the width of the straight portion of the “]”-shaped pattern of the resultant interconnect from being made smaller than the design width.
    Type: Grant
    Filed: October 24, 2000
    Date of Patent: June 11, 2002
    Assignee: NEC Corporation
    Inventor: Keiichiro Tounai
  • Publication number: 20020047089
    Abstract: An optical proximity effect correcting method in a semiconductor manufacturing process includes adding, detecting, judging, and deleting. The adding includes adding a first correcting region around a portion of a first design pattern. The portion faces a second design pattern. A first corrected design pattern includes the first correcting region and the first design pattern. The detecting includes detecting a space between the first corrected design pattern and the second design pattern. The judging includes judging whether the space is smaller than or equal to a predetermined value. The deleting includes deleting at least a portion of the first correcting region such that the space is larger than the predetermined value, when the space is smaller than or equal to the predetermined value.
    Type: Application
    Filed: December 4, 2001
    Publication date: April 25, 2002
    Inventors: Keiichiro Tounai, Takeshi Hamamoto
  • Publication number: 20020043615
    Abstract: An optical proximity effect correcting method in a semiconductor manufacturing process includes adding, detecting, judging, and deleting. The adding includes adding a first correcting region around a portion of a first design pattern. The portion faces a second design pattern. A first corrected design pattern includes the first correcting region and the first design pattern. The detecting includes detecting a space between the first corrected design pattern and the second design pattern. The judging includes judging whether the space is smaller than or equal to a predetermined value. The deleting includes deleting at least a portion of the first correcting region such that the space is larger than the predetermined value, when the space is smaller than or equal to the predetermined value.
    Type: Application
    Filed: December 4, 2001
    Publication date: April 18, 2002
    Inventors: Keiichiro Tounai, Takeshi Hamamoto
  • Publication number: 20010034877
    Abstract: To provide a photomask pattern shape correction method for suitably modifying and correcting a pattern deformation caused by a optical proximity effect. A corner 1 is extracted where an exterior angle of a wiring layer pattern is an angle of 90 degrees, which is out of a diffusion layer and where the distance R from the gate is within the predetermined value Rm and the interval between the gates is equal to or more than a set value Pm. A correction figure (A)11 is added to a side in the gate direction of this corner 1 and a correction figure (B)12 to the side not in the gate direction, and the interval G1 between the correction figure (B)12 and an adjacent correction figure is calculated, and the interval G1 calculated is checked whether it is equal to or more than the set value G1m.
    Type: Application
    Filed: April 19, 2001
    Publication date: October 25, 2001
    Inventor: Keiichiro Tounai
  • Patent number: 6174633
    Abstract: A method for correcting a photo-contiguous effect during manufacture of a semiconductor device comprising the steps of: designating a first peripheral region surrounding a first layer; locating at least a corner of a second layer belonging to the first peripheral region; forming a second peripheral region surrounding the corner; and adding the second peripheral region to the first layer is disclosed. The method can suppress not only increase of the data and of a period of time for correcting the photo-contiguous effect but also deterioration of resolution can be prevented.
    Type: Grant
    Filed: November 17, 1999
    Date of Patent: January 16, 2001
    Assignee: NEC Corporation
    Inventor: Keiichiro Tounai
  • Patent number: 5871874
    Abstract: In a method for forming a mask pattern which is exposed with light or electrons, a resist layer being exposed with light or electrons passed through said mask pattern to form a resist pattern, a light or electron beam intensity on the resist layer is calculated. Then, a deviation of a logarithmic value of the light intensity is calculated, and a ratio of a logarithmic value of a dissolving speed of the resist layer to a logarithmic value of the exposure is calculated. Then, a value is calculated by a.sup.1/b. I where a is the deviation, b is the ratio, I is the intensity. Then, a size of the resist pattern is calculated by setting a contour having a predetermined value in a distribution of the value, and a difference between the mask pattern and the size of the resist pattern is calculated. Finally, the mask pattern is corrected in accordance with the difference.
    Type: Grant
    Filed: August 27, 1997
    Date of Patent: February 16, 1999
    Assignee: NEC Corporation
    Inventor: Keiichiro Tounai
  • Patent number: 5627083
    Abstract: A method of fabricating a semiconductor device includes the steps of forming an inner circuit, a cell test pattern, and a superposition error measurement pattern. The inner circuit includes a plurality of recurring basic cells. The cell test pattern includes a test cell array having at least one test basic cell of the same design as the basic cells in the inner circuit and a plurality of test dummy cells disposed around the test cell array. The superposition error measurement pattern includes a first and a second pattern formed in the steps of a first and a second lithographic step, respectively, performed in the formation of the basic cells. The inner circuit, said cell test pattern and said superposition error measure pattern are integrated on the same semiconductor substrate.
    Type: Grant
    Filed: May 12, 1995
    Date of Patent: May 6, 1997
    Assignee: NEC Corporation
    Inventor: Keiichiro Tounai
  • Patent number: 5357312
    Abstract: The invention relates to an illuminating system in an exposure apparatus used for the fabrication of semiconductor devices to transfer a pattern on a reticle to a substrate having a photosensitive surface. As is usual, the illuminating system has reflecting and collimating elements to form light rays emitted from a light source into a light beam circular in cross-sectional shape, an optical integrater to uniformalize the light beam and an aperture diaphragm to desirably shape the uniformalized light beam. A reducing or magnifying lens, which is interchangeable with another reducing or magnifying lens different in reducing or magnifying power, is added in oreder to vary the diameter of the light beam nearly in conformance with the aperture diameter before the beam arrives at the aperture diaphragm to thereby reduce a loss of illuminating light by blockage by the aperture diaphragm.
    Type: Grant
    Filed: September 28, 1993
    Date of Patent: October 18, 1994
    Assignee: NEC Corporation
    Inventor: Keiichiro Tounai