Patents by Inventor Keiichiro Wakamiya
Keiichiro Wakamiya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7141879Abstract: There is described an improved semiconductor device of chip-scale package (CSP) comprising posts provided on respective electrode pads of a semiconductor chip, and solder balls which are provided on the respective posts as external terminals after the semiconductor chip has been encapsulated with resin while the posts are held in a projecting manner. The semiconductor device prevents occurrence of cracks, which would otherwise be caused by stress which is induced by a difference in coefficient of linear expansion between the semiconductor chip and the sealing resin and is imposed on the posts. In order to alleviate the stress imposed on the posts, a stress-absorbing layer formed from a metal layer having a low Young's modulus, such as gold (Au) or palladium (Pd), is interposed in the middle of each of the posts.Type: GrantFiled: March 28, 2001Date of Patent: November 28, 2006Assignee: Renesas Technology Corp.Inventors: Keiichiro Wakamiya, Satoshi Yamada
-
Patent number: 6777814Abstract: A semiconductor device includes a semiconductor chip, and a circuit substrate disposed such that the circuit substrate faces the semiconductor chip and is electrically connected to the semiconductor chip through a connection conductor. A pad electrode and a terminal electrode are formed on a surface of the semiconductor chip and a surface of the circuit substrate, respectively. The connection conductor is connected between the pad electrode and the terminal electrode. The surface of the semiconductor and the surface of the circuit substrate face each other. A conductive dummy pattern is formed on the facing surface of the semiconductor chip or the circuit substrate. A space between the facing surfaces is filled with nonconductive resin. With this arrangement, it is possible to make uniform the temperature distribution between the facing surfaces, thereby making the temperature and the viscosity of the nonconductive resin uniform to reduce attenuation of ultrasonic waves.Type: GrantFiled: June 14, 2002Date of Patent: August 17, 2004Assignee: Renesas Technology Corp.Inventors: Toshihiro Iwasaki, Michitaka Kimura, Keiichiro Wakamiya, Yasumichi Hatanaka
-
Patent number: 6756686Abstract: A semiconductor device includes a first substrate, a second substrate, a plurality of conductors, and supporting members. The first substrate has a plurality of electrode portions disposed on one side thereof. The second substrate has a plurality of electrode portions disposed on one side thereof. The conductors are for connecting the plurality of electrode portions of the first substrate to the plurality of electrode portions of the second substrate. The supporting members supporting the first substrate and the second substrate are disposed on a location where resonance caused by ultrasonic oscillation externally supplied is restrained in the state where the first substrate is connected to the second substrate. The supporting members prevent irregular oscillation and resonance caused by the ultrasonic oscillation.Type: GrantFiled: August 21, 2002Date of Patent: June 29, 2004Assignee: Renesas Technology Corp.Inventors: Toshihiro Iwasaki, Keiichiro Wakamiya, Michitaka Kimura, Yasumichi Hatanaka
-
Patent number: 6677677Abstract: The semiconductor device has a flip chip structure. The chip is electrically connected to the chip mounting member via function bumps provided on the chip. Dummy bumps acting against a local bending force of the chip are interposed between the chip and the chip mounting member.Type: GrantFiled: March 27, 2002Date of Patent: January 13, 2004Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Michitaka Kimura, Toshihiro Iwasaki, Yasumichi Hatanaka, Keiichiro Wakamiya
-
Publication number: 20030111742Abstract: The present invention comprises: a semiconductor chip; a circuit substrate disposed such that the circuit substrate faces the semiconductor chip and is electrically connected to the semiconductor chip through a connection conductor; a pad electrode and a terminal electrode formed on a surface of the semiconductor chip and a surface of the circuit substrate, respectively, and having the connection conductor connected thereto, the surface of the semiconductor and the surface of the circuit substrate facing each other; nonconductive resin formed such that the nonconductive resin fills a space between the facing surfaces; and a conductive dummy pattern formed on the facing surface of the semiconductor chip or the circuit substrate, the conductive dummy pattern having a predetermined shape.Type: ApplicationFiled: June 14, 2002Publication date: June 19, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Toshihiro Iwasaki, Michitaka Kimura, Keiichiro Wakamiya, Yasumichi Hatanaka
-
Publication number: 20030060035Abstract: The semiconductor device has a flip chip structure. The chip is electrically connected to the chip mounting member via function bumps provided on the chip. Dummy bumps acting against a local bending force of the chip are interposed between the chip and the chip mounting member.Type: ApplicationFiled: March 27, 2002Publication date: March 27, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Michitaka Kimura, Toshihiro Iwasaki, Yasumichi Hatanaka, Keiichiro Wakamiya
-
Publication number: 20030057537Abstract: A semiconductor device includes a first substrate, a second substrate, a plurality of conductors, and supporting members. The first substrate has a plurality of electrode portions disposed on one side thereof. The second substrate has a plurality of electrode portions disposed on one side thereof. The conductors are for connecting the plurality of electrode portions of the first substrate to the plurality of electrode portions of the second substrate. The supporting members supporting the first substrate and the second substrate are disposed on a location where resonance caused by ultrasonic oscillation externally supplied is restrained in the state where the first substrate is connected to the second substrate. The supporting members prevent irregular oscillation and resonance caused by the ultrasonic oscillation.Type: ApplicationFiled: August 21, 2002Publication date: March 27, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Toshihiro Iwasaki, Keiichiro Wakamiya, Michitaka Kimura, Yasumichi Hatanaka
-
Publication number: 20030057569Abstract: A semiconductor device is used which is provided with a semiconductor chip having Au bumps on its surface and a chip-mounting substrate having external electrode lands on its chip-mounting face while having external electrode pads on its external connection face and constituted by bonding Au bumps on the semiconductor chip to internal electrode pads on the chip-mounting substrate while turning the semiconductor chip upside down, in which external electrode lands are arranged in areas corresponding to arrangement areas of internal electrode pads at the both sides of the chip-mounting substrate.Type: ApplicationFiled: March 6, 2002Publication date: March 27, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Keiichiro Wakamiya, Toshihiro Iwasaki, Michitaka Kimura, Yasumichi Hatanaka
-
Patent number: 6404059Abstract: A semiconductor device comprises an insulated circuit board which includes a terminal electrode disposed on the rear surface or at a plane between the rear surface and the front surface thereof. An opening is formed in the insulating circuit board in such a manner as to reach the terminal electrode. A semiconductor substrate including an electrode pad is mounted on the insulated circuit board in such a manner that the electrode pad faces to the terminal electrode. A non-conductive resin is interposed in a gap between the semiconductor substrate and the insulated circuit board. The electrode pad on the semiconductor substrate is electrically connected to the terminal electrode via a connecting conductor inserted in the opening.Type: GrantFiled: July 11, 2000Date of Patent: June 11, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Toshihiro Iwasaki, Keiichiro Wakamiya
-
Publication number: 20020041013Abstract: There is described an improved semiconductor device of chip-scale package (CSP) comprising posts provided on respective electrode pads of a semiconductor chip, and solder balls which are provided on the respective posts as external terminals after the semiconductor chip has been encapsulated with resin while the posts are held in a projecting manner. The semiconductor device prevents occurrence of cracks, which would otherwise be caused by stress which is induced by a difference in coefficient of linear expansion between the semiconductor chip and the sealing resin and is imposed on the posts. In order to alleviate the stress imposed on the posts, a stress-absorbing layer formed from a metal layer having a low Young's modulus, such as gold (Au) or palladium (Pd), is interposed in the middle of each of the posts.Type: ApplicationFiled: March 28, 2001Publication date: April 11, 2002Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Keiichiro Wakamiya, Satoshi Yamada