Abstract: A design method of a semiconductor integrated circuit sets an area having apices of opposing corners of a position of a start point logic cell and a position of an end point logic cell to a repeater search area, adds free area information to the repeater search area, sets a drive boundary in the repeater search area based on a drive ability of the start point logic cell, searches a repeater candidate that can be arranged in an area of the drive boundary based on the free area information, calculates a delay time from the start point logic cell to the end point logic cell based on delay time information and a coordinate of the repeater candidate that is searched, and determines a repeater arranged between the start point logic cell and the end point logic cell from the repeater candidate based on the delay time that is calculated.

Abstract: A design method of a semiconductor integrated circuit sets an area having apices of opposing corners of a position of a start point logic cell and a position of an end point logic cell to a repeater search area, adds free area information to the repeater search area, sets a drive boundary in the repeater search area based on a drive ability of the start point logic cell, searches a repeater candidate that can be arranged in an area of the drive boundary based on the free area information, calculates a delay time from the start point logic cell to the end point logic cell based on delay time information and a coordinate of the repeater candidate that is searched, and determines a repeater arranged between the start point logic cell and the end point logic cell from the repeater candidate based on the delay time that is calculated.

Abstract: A design method of a semiconductor device comprising forming a base wafer by using a plurality of semiconductor chips including a plurality of functional macros, generating macro test information by testing the plurality of function macros of the plurality of semiconductor devices; and picking a macro that is prohibited from being used out of the plurality of function macros based on the macro test information and a net list of user circuit. Since tests are carried out at the phase of a base wafer, it is possible to improve yield rates in the manufacture of semiconductor integrated circuits.

Abstract: A semiconductor integrated circuit apparatus relates to a structured ASIC that wires functional cells in a common wiring layer, which is not dependent on a user circuit and common to several sorts, and a customized layer provided over the common wiring layer to form the user circuit. In the semiconductor integrated circuit apparatus, a functional cell constituting a sequential circuit such as a flip-flop and a functional cell constituting a combinational circuit are placed in matrix of column and row. Further, the functional cell constituting the sequential circuit is placed obliquely in the matrix.

Abstract: A semiconductor integrated circuit apparatus relates to a structured ASIC that wires functional cells in a common wiring layer, which is not dependent on a user circuit and common to several sorts, and a customized layer provided over the common wiring layer to form the user circuit. In the semiconductor integrated circuit apparatus, a functional cell constituting a sequential circuit such as a flip-flop and a functional cell constituting a combinational circuit are placed in matrix of column and row. Further, the functional cell constituting the sequential circuit is placed obliquely in the matrix.

Abstract: A semiconductor device having internal power terminals including a positive power terminal supplying a high potential and a negative power terminal supplying a low potential to the internal device region of a semiconductor chip in which the positive power terminal and the negative power terminal are arranged uniformly in the internal device region of the semiconductor chip and power is supplied from the outside of the semiconductor chip to the internal power terminal, wherein a metalizing metal of the same layer as the internal power terminal is wired between the internal power terminals in a tandem shape so as to be connected to the internal power terminal of the same.

Abstract: A semiconductor device having an internal power terminal including a positive power terminal supplying a high potential and a negative power terminal supplying a low potential to the internal device region of a semiconductor chip in which the positive power terminal and the negative power terminal are arranged uniformly in the internal device region of the semiconductor chip and power is supplied from the outside of the semiconductor chip to the internal power terminal, wherein a metalizing metal of the same layer as the internal power terminal is wired between the internal power terminals in a tandem shape so as to be connected to the internal power terminal of the same potential, a top and under layer connection VIA is provided in the position where the tandem metalizing metal wire and an under layer metalizing metal cross so as to supply power to the power wire of the internal device region made of the under layer metalizing metal, and only one metalizing metal layer of the same layer as a power source PAD

Abstract: In a method for dividing a terminal into a plurality of terminal units in automatic interconnect routing processing in a semiconductor device, a terminal portion, which is a part of the terminal, overlapped an intersection of the wiring grids in X-direction and Y-direction is extracted. A terminal region which includes the terminal portion is surrounded with a top side, a bottom side, a left side and a right side of the terminal region. These sides are moved outward so as to expand the terminal region, respectively, thereby dividing the terminal into a plurality of terminal regions.

Abstract: A data processing system for designing a customized master slice data includes the steps of consecutively locating a cell base block based on the design data, a plurality of dummy gate blocks, and a possible number of intermediate blocks in the area of the semiconductor chip; replacing dummy gate blocks by gate array blocks while shifting the gate array blocks by half length; and locating intermediate blocks in an area generated by shifting the gate array blocks. The space between the gate array block and the cell base block is filled with the intermediate blocks for preventing interference therebetween.

Abstract: In a method for dividing a terminal into a plurality of terminal units in automatic interconnect routing processing in a semiconductor device, a terminal portion, which is a part of the terminal, overlapped an intersection of the wiring grids in X-direction and Y-direction is extracted. A terminal region which includes the terminal portion is surrounded with a top side, a bottom side, a left side and a right side of the terminal region. These sides are moved outward so as to expand the terminal region, respectively, thereby dividing the terminal into a plurality of terminal regions.