Abstract: Provided are a PDP device and a drive method thereof which restrict the generation of an erroneous discharge in the all-cell reset period and to restrict the appearance of flickers in the areas with low grayscale levels even if some areas have a lower firing voltage than the other areas due to variation of a property in the panel surfaces or due to a long-term driving, or even if the voltage applied to the address electrode is increased with the pursuit of high definition. The pulse Pul.3 is applied to address electrodes Dat at timing t0 prior to timing t1 when the potential of the scan electrodes Scn is increased to Vq(V). In this drive method, voltage Vx(V) is applied to address electrodes Dat so that there is no potential difference between the scan electrodes Scn and the sustain electrodes Sus at timing t0 when discharge Dis.3 is generated. Accordingly, the discharge Dis.

Abstract: A bypass control section (6) maintains a bypass switch (5) in the ON state during the period when a battery voltage (Vi) is higher than the output voltage (Vo) to an external load (L). Upon falling of the output voltage (Vo) at a desired voltage (ET), a converter control section (4) starts switching control at once, and a step-up chopper (3) promptly starts boost operation. The bypass control section (6) maintains the bypass switch (5) in the ON state from the start of the boost operation of the step-up chopper (3) until the match between the battery voltage (Vi) and the output voltage (Vo).

Abstract: A bypass control section (6) maintains a bypass switch (5) in the ON state during the period when a battery voltage (Vi) is higher than the output voltage (Vo) to an external load (L). Upon falling of the output voltage (Vo) at a desired voltage (ET), a converter control section (4) starts switching control at once, and a step-up chopper (3) promptly starts boost operation. The bypass control section (6) maintains the bypass switch (5) in the ON state from the start of the boost operation of the step-up chopper (3) until the match between the battery voltage (Vi) and the output voltage (Vo).

Abstract: A circuit in an electronic keyboard musical instrument for preferentially selecting the highest and lowest tones from among the tones in chords produced by keys on the keyboard which have been struck. The circuit has a set of series connected resistors having equal values, the number of resistors in the set corresponding to the number of tones from which the highest and lowest tones are to be selected. An end resistor is connected between each end of the set of resistors and a reference voltage level. A plurality of transistors corresponding to the number of resistors each has the emitter thereof connected to the set of resistors between the corresponding resistor and the resistor corresponding to the next adjacent transistor, and has the collector thereof adapted to receive a corresponding tone signal. A keyswitch is connected to the base of each transistor and to a bias source.