Abstract: A microcomputer provided with a direct memory access (DMA) controller comprises a central processing unit (CPU), which includes a CPU timing controller, an address computation section, and an address bus output buffer coupled between the output of the address computation section and an external address bus. The CPU also includes an auxiliary timing controller operative, in response to a hold request from a DMA controller, to output a HOLD acknowledge (HOLDA) signal to the DMA controller and to reset a BUS ENABLE signal to the address bus output buffer, so tha the CPU is isolated from the external address bus. The CPU further includes an address latch circuit connected between the output of the address computation section and the address bus output buffer to temporarily hold the address output in response to a latch signal from the auxiliary timing controller, so that the address output is supplied to the address bus immediately when the latch signal is reset at the termination of the DMA operation.