Abstract: A clock generation circuit includes a phase comparator inputted with a reference clock and a feedback clock, a current controlled oscillator for generating a clock frequency according to an output of the phase comparator, a frequency dividing circuit for dividing the clock frequency by a frequency dividing rate based on a frequency dividing rate setting signal to produce a feedback clock, and a control circuit for counting the clock frequency and outputting a control current setting signal that sets a control current of the current controlled oscillator and the frequency dividing rate setting signal based on a count value.

Abstract: A phase-locked loop circuit has a DLL circuit in a stage preceding an analog PLL circuit. The DLL circuit detects a phase difference between a reference clock signal and a feedback signal, changes the detected phase difference to a phase difference increased so as to be greater than a steady state phase error which the analog PLL circuit has, and supplies the resultant phase difference to the analog PLL circuit. While the phase difference between the reference clock signal and the feedback signal is being detected by the DLL circuit, the analog PLL circuit operates to reduce the increased phase difference to the steady state phase error. As a result, the phase difference between the reference clock signal and the feedback signal is reduced to a sensitivity limit of a phase comparator in the DLL circuit.

Abstract: A phase-locked loop circuit has a DLL circuit in a stage preceding an analog PLL circuit. The DLL circuit detects a phase difference between a reference clock signal and a feedback signal, changes the detected phase difference to a phase difference increased so as to be greater than a steady state phase error which the analog PLL circuit has, and supplies the resultant phase difference to the analog PLL circuit. While the phase difference between the reference clock signal and the feedback signal is being detected by the DLL circuit, the analog PLL circuit operates to reduce the increased phase difference to the steady state phase error. As a result, the phase difference between the reference clock signal and the feedback signal is reduced to a sensitivity limit of a phase comparator in the DLL circuit.

Abstract: A phase-locked loop circuit includes with an oscillator which outputs a pulse signal, and a frequency divider for frequency-dividing the pulse signal. The frequency divider includes with a dividing factor switching circuit which switches the dividing factor before a phase of the pulse signal is locked to that of a reference clock signal.

Abstract: A phase-locked loop circuit is provided with an oscillator which outputs a pulse signal, and a frequency divider for frequency-dividing the pulse signal. The frequency divider is provided with a dividing factor switching circuit which switches the dividing factor before a phase of the pulse signal is locked to that of a reference clock signal.