Patents by Inventor Keiji Miyamoto

Keiji Miyamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6104972
    Abstract: A background heat source unit 4 having a plurality of heat sources, which are arranged substantially at a fixed interval and set to a temperature different from the body temperature of passenger and also from the ambient temperature, and an infrared sensor 7, are disposed such that they face each other via a passenger. Whether a passenger is present is checked according to the result of a check, made by comparing a detected temperature pattern of the background heat source unit 4, detected by the infrared sensor 7, and a reference temperature pattern of the background heat source unit 4, preliminarily stored in a control circuit 17, as to whether a non-identical area is present in the compared temperature patterns.
    Type: Grant
    Filed: October 22, 1998
    Date of Patent: August 15, 2000
    Assignee: NEC Corporation
    Inventors: Keiji Miyamoto, Masahiko Sano, Naoki Oda, Junshiro Motoyama
  • Patent number: 5650052
    Abstract: Sputtering apparatus and method suitable for forming a step coating on a workpiece. A workpiece is supported in a chamber, particles are emitted from a sputtering source, and the particles are passed through a collimating filter having a plurality of transmissive cells positioned between the sputtering source and the workpiece to limit the angles at which the particles can be deposited onto the workpiece. The collimating filter varies in height from a center portion to an outer portion while preferably maintaining a constant cell aspect ratio.
    Type: Grant
    Filed: October 4, 1995
    Date of Patent: July 22, 1997
    Inventors: Sergio Edelstein, Nitin Khurana, Keiji Miyamoto, Roderick C. Mosely, William J. Murphy, Vijay Parkhe, James Van Gogh, Robert S. West
  • Patent number: 5067008
    Abstract: An IC package comprising an integrated substrate which includes a cavity, in which an IC chip is mounted, formed by a wall surrounding the IC chip, and a groove formed in the surrounding wall extending to surround and communicate with the cavity and method for fabricating the IC package, wherein an excessive amount of resin is filled in the cavity of the integrated substrate, and the composite structure pressed by a plate whereby the excess of the resin overflows from the cavity pressure to be received in the groove such that, the exposed surface of the filled resin is formed into a predetermined shape without requiring grinding.
    Type: Grant
    Filed: August 7, 1990
    Date of Patent: November 19, 1991
    Assignee: Hitachi Maxell, Ltd.
    Inventors: Yoshimi Yanaka, Keiji Miyamoto
  • Patent number: 4910582
    Abstract: This invention concerns a semiconductor device of a tape carrier type and a method of manufacturing the same, wherein electroconductive layers made of the same material as that of lead terminals are disposed so as to substantially surround the circumferential edge of a hole for containing an IC chip with a predetermined gap as barrier portions for controlling the flowing range or the coating range on a carrier tape before coagulation of the coating material when the surface of said IC chip after being inserted into the IC chip-containing hole and connected with the lead terminals is coated with the coating material. The steps formed with the surface of the carrier tape and the barrier portions which substantially surround the circumferential edge of the hole at a predetermined gap thereby results in controlling the flowing range of the coating material before coagulation by which the coating region on the surface of the IC chip, etc.
    Type: Grant
    Filed: April 18, 1989
    Date of Patent: March 20, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Keiji Miyamoto, Atsushi Nakamura, Tsuneo Satoh, Kazuo Kojima, Masayuki Morita
  • Patent number: 4822989
    Abstract: This invention concerns a semiconductor device of a tape carrier type and a method of manufacturing the same, wherein electroconductive layers made of the same material as that of lead terminals are disposed so as to substantially surround the circumferential edge of a hole for containing an IC chip with a predetermined gap as barrier portions for controlling the flowing range or the coating range on a carrier tape before coagulation of the coating material when the surface of said IC chip after being inserted into the IC chip-containing hole and connected with the lead terminals is coated with the coating material. The steps formed with the surface of the carrier tape and the barrier portions which substantially surround the circumferential edge of the hole at a predetermined gap thereby results in controlling the flowing range of the coating material before coagulation, by which the coating region on the surface of the IC chip, etc.
    Type: Grant
    Filed: May 21, 1987
    Date of Patent: April 18, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Keiji Miyamoto, Atsushi Nakamura, Tsuneo Satoh, Kazuo Kojima, Masayuki Morita
  • Patent number: 4042726
    Abstract: A method for manufacturing a semiconductor device wherein semiconductor material is selectively removed from a principal surface of a semiconductor substrate having at least one semiconductor layer formed thereon to provide a groove that extends through said layer and into the substrate and wherein the semiconductor material of the substrate is selectively oxidized to form an oxide insulator layer within the groove. The groove has a width which is smaller than the thickness of the semiconductor layer and the oxide insulator layer serves to isolate a portion of the semiconductor layer from adjacent portions of the substrate.
    Type: Grant
    Filed: September 8, 1975
    Date of Patent: August 16, 1977
    Assignee: Hitachi, Ltd.
    Inventors: Tadao Kaji, Tsuneaki Kamei, Keiji Miyamoto
  • Patent number: 3997378
    Abstract: In the manufacture of a semiconductor device, when an epitaxially-grown layer is formed on a semiconductor substrate partially formed with an oxide, a polycrystalline layer is formed on the oxide; the polycrystalline part is used as an isolation region for elements to be formed in the epitaxially-grown layer. The oxide for growing the polycrystalline layer is buried and formed in the semiconductor substrate at a depth at which a breakdown voltage between the elements is attained, whereby the width of the isolation region can be made small, so as to increase the density of integration of the semiconductor device.
    Type: Grant
    Filed: October 17, 1975
    Date of Patent: December 14, 1976
    Assignee: Hitachi, Ltd.
    Inventors: Tadao Kaji, Tsuneaki Kamei, Keiji Miyamoto