Patents by Inventor Keiji Nunomura

Keiji Nunomura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7847481
    Abstract: Ribs for defining pixel cells are formed in the shape of a lattice, and sustain electrodes and scan electrodes are disposed near the ribs. The electrodes are spaced apart in each pixel cell, and the sustain electrode and the scan electrode are each cut away between pixel cells arranged in the row direction to provide each pixel cell with individually separated electrodes. In addition, between pixel cells adjacent to each other in the row direction, the sustain electrodes and the scan electrodes are connected to each other by means of a sustain-side bus electrode and a scan-side bus electrode, respectively. This makes it possible to provide a high luminous efficiency. Furthermore, each pixel cell is provided with a wide distance between the electrodes and thereby with a large effective opening portion. Thus, this provides only a small amount of reduction in intensity when the electrodes are spaced apart between the pixel cells arranged in the row direction in order to increase the luminous efficiency.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: December 7, 2010
    Assignee: Panasonic Corporation
    Inventors: Yoshio Sano, Nobumitsu Aibara, Yoshiaki Yanai, Toshiyuki Akiyama, Tetsumasa Okamoto, Kazuaki Yanagida, Hirokazu Tateno, Naoto Hirano, Yoshito Tanaka, Tadashi Nakamura, Keiji Nunomura
  • Publication number: 20080084161
    Abstract: Ribs for defining pixel cells are formed in the shape of a lattice, and sustain electrodes and scan electrodes are disposed near the ribs. The electrodes are spaced apart in each pixel cell, and the sustain electrode and the scan electrode are each cut away between pixel cells arranged in the row direction to provide each pixel cell with individually separated electrodes. In addition, between pixel cells adjacent to each other in the row direction, the sustain electrodes and the scan electrodes are connected to each other by means of a sustain-side bus electrode and a scan-side bus electrode, respectively. This makes it possible to provide a high luminous efficiency. Furthermore, each pixel cell is provided with a wide distance between the electrodes and thereby with a large effective opening portion. Thus, this provides only a small amount of reduction in intensity when the electrodes are spaced apart between the pixel cells arranged in the row direction in order to increase the luminous efficiency.
    Type: Application
    Filed: October 31, 2007
    Publication date: April 10, 2008
    Applicants: NEC Corporation
    Inventors: Yoshio SANO, Nobumitsu Aibara, Yoshiaki Yanai, Toshiyuki Akiyama, Tetsumasa Okamoto, Kazuaki Yanagida, Hirokazu Tateno, Naoto Hirano, Yoshito Tanaka, Tadashi Nakamura, Keiji Nunomura
  • Patent number: 7336033
    Abstract: Ribs for defining pixel cells are formed in the shape of a lattice, and sustain electrodes and scan electrodes are disposed near the ribs. The electrodes are spaced apart in each pixel cell, and the sustain electrode and the scan electrode are each cut away between pixel cells arranged in the row direction to provide each pixel cell with individually separated electrodes. In addition, between pixel cells adjacent to each other in the row direction, the sustain electrodes and the scan electrodes are connected to each other by means of a sustain-side bus electrode and a scan-side bus electrode, respectively. This makes it possible to provide a high luminous efficiency. Furthermore, each pixel cell is provided with a wide distance between the electrodes and thereby with a large effective opening portion. Thus, this provides only a small amount of reduction in intensity when the electrodes are spaced apart between the pixel cells arranged in the row direction in order to increase the luminous efficiency.
    Type: Grant
    Filed: October 14, 2005
    Date of Patent: February 26, 2008
    Assignee: Pioneer Corporation
    Inventors: Yoshio Sano, Nobumitsu Aibara, Yoshiaki Yanai, Toshiyuki Akiyama, Tetsumasa Okamoto, Kazuaki Yanagida, Hirokazu Tateno, Naoto Hirano, Yoshito Tanaka, Tadashi Nakamura, Keiji Nunomura
  • Publication number: 20070278955
    Abstract: A manufacturing method of a PDP includes: a first material filling step for filling recessed portions (41) of a molding die (4) with a first dielectric paste (23A) that forms partitions; a second material application step for applying a second dielectric paste (22A) that forms an address electrode protective layer on a rear substrate (2); a transfer step for pressing the molding die (4) against the second dielectric paste (22A) and then peeling the molding die (4) off from the rear substrate (2); and a firing step. Since the molding die (4) is pressed against the second dielectric paste (22A) that has a fluidity in the transfer step, the first dielectric paste (23A) and the second dielectric paste (22A) can be adhered to each other securely. Accordingly, the partitions having a desired shape can be formed securely and inter-partition portions of the address electrode protective layer can be uniformly formed with a uniform thickness.
    Type: Application
    Filed: April 4, 2007
    Publication date: December 6, 2007
    Applicants: PIONEER CORPORATION, Advanced PDP Development Center Corporation
    Inventors: Yoshihiko Kusuma, Yuji Ito, Youichi Ikarashi, Keiji Nunomura, Toshihiko Kogure, Osamu Oida, Takahiro Kobayashi
  • Patent number: 7023406
    Abstract: To provide a plasma display device which implements a peak luminance higher than prior art, reduces the power dissipation, improves the smoothness of gradation display, and conducts clear display suitable especially for TV display. By setting a plurality of APL levels according to the average value of the scene brightness, and by shortening a sustaining pulse period and increasing the number of sustaining pulses of each sub-field in APL levels having small APL, the peak luminance is raised. Further, by making the sustaining pulse period long in APL levels having large APL requiring large discharge light emission power, the light emission efficiency is improved and the maximum power dissipation is reduced. The luminance distribution in the scene when the APL level is small is detected. On the basis of that information, setting of the number of sustaining pulses and the sustaining pulse period is changed in the same APL level.
    Type: Grant
    Filed: May 9, 2000
    Date of Patent: April 4, 2006
    Assignee: NEC Corporation
    Inventors: Keiji Nunomura, Yoshio Sano, Toshiyuki Akiyama, Hachiro Yamada
  • Patent number: 7002296
    Abstract: Ribs for defining pixel cells are formed in the shape of a lattice, and sustain electrodes and scan electrodes are disposed near the ribs. The electrodes are spaced apart in each pixel cell, and the sustain electrode and the scan electrode are each cut away between pixel cells arranged in the row direction to provide each pixel cell with individually separated electrodes. In addition, between pixel cells adjacent to each other in the row direction, the sustain electrodes and the scan electrodes are connected to each other by means of a sustain-side bus electrode and a scan-side bus electrode, respectively. This makes it possible to provide a high luminous efficiency.
    Type: Grant
    Filed: July 23, 2001
    Date of Patent: February 21, 2006
    Assignee: Pioneer Corporation
    Inventors: Yoshio Sano, Nobumitsu Aibara, Yoshiaki Yanai, Toshiyuki Akiyama, Tetsumasa Okamoto, Kazuaki Yanagida, Hirokazu Tateno, Naoto Hirano, Yoshito Tanaka, Tadashi Nakamura, Keiji Nunomura
  • Publication number: 20060033436
    Abstract: Ribs for defining pixel cells are formed in the shape of a lattice, and sustain electrodes and scan electrodes are disposed near the ribs. The electrodes are spaced apart in each pixel cell, and the sustain electrode and the scan electrode are each cut away between pixel cells arranged in the row direction to provide each pixel cell with individually separated electrodes. In addition, between pixel cells adjacent to each other in the row direction, the sustain electrodes and the scan electrodes are connected to each other by means of a sustain-side bus electrode and a scan-side bus electrode, respectively. This makes it possible to provide a high luminous efficiency. Furthermore, each pixel cell is provided with a wide distance between the electrodes and thereby with a large effective opening portion. Thus, this provides only a small amount of reduction in intensity when the electrodes are spaced apart between the pixel cells arranged in the row direction in order to increase the luminous efficiency.
    Type: Application
    Filed: October 14, 2005
    Publication date: February 16, 2006
    Inventors: Yoshio Sano, Nobumitsu Aibara, Yoshiaki Yanai, Toshiyuki Akiyama, Tetsumasa Okamoto, Kazuaki Yanagida, Hirokazu Tateno, Naoto Hirano, Yoshito Tanaka, Tadashi Nakamura, Keiji Nunomura
  • Patent number: 6744413
    Abstract: First and second substrates are disposed oppositely to each other in a plasma display panel. A parallel-crossed partition wall, a plurality of bus electrodes, a plurality of display discharge electrodes, and a plurality of data electrodes are provided to the panel. The parallel-crossed partition wall defines a space between the first and second substrates into a plurality of display cells. The bus electrodes are provided in a side of the first substrate opposite the second substrate, and superposed on a portion of the partition wall extended in the line direction when seen from a plane. The display discharge electrodes each are extended from each of the bus electrodes in each of the display cells defined in the columnar direction by a portion of the partition wall overlapping with the bus electrode when seen from the plane. The data electrodes are provided in a side of the second substrate opposite the first substrate and extended in the columnar direction.
    Type: Grant
    Filed: December 20, 2000
    Date of Patent: June 1, 2004
    Assignee: NEC Corporation
    Inventor: Keiji Nunomura
  • Patent number: 6614412
    Abstract: To provide a plasma display panel which improves the write characteristics, luminous luminance, and luminous efficiency and which has a longer life. On a back glass substrate, data electrodes are formed in the substrate column direction. Over the data electrodes, a dielectric layer is formed. On the dielectric layer, scan electrodes are formed in a substrate row direction. Over the scan electrodes, a dielectric layer is formed. On the dielectric layer, partitions are formed in the substrate column direction. On the dielectric layer including the partitions, a protection layer and a fluorescent material layer are formed. On the other hand, on a front glass substrate, common electrodes and bus electrodes electrically connected to the common electrodes are formed in the substrate row direction so as to be opposed to the scan electrodes. Over the common electrodes and the bus electrodes, a dielectric layer and a protection layer are formed.
    Type: Grant
    Filed: August 29, 2000
    Date of Patent: September 2, 2003
    Assignee: NEC Corporation
    Inventors: Naoto Hirano, Keiji Nunomura
  • Patent number: 6498594
    Abstract: A plasma display panel in which deterioration of luminance accompanied by an increase in resolution can be improved. The plasma display panel comprises a plurality of center slit surface discharge electrodes extending in a first direction, each of the center slit surface discharge electrodes having a pair of surface discharge electrode portions formed of a pair of transparent electrodes and a bus electrode which electrically couples said pair of transparent electrodes with each other, and a center slit between the surface discharge electrode portions. A plurality of data electrodes extend in a second direction which crosses the first direction of extension of the center slit surface discharge electrodes. A surface discharge gap is formed between adjacent the center slit surface discharge electrodes.
    Type: Grant
    Filed: November 16, 1999
    Date of Patent: December 24, 2002
    Assignee: NEC Corporation
    Inventor: Keiji Nunomura
  • Patent number: 6479932
    Abstract: Described herein is an AC plasma display panel in which a discharge part is separated from a bus electrode and a partition wall. In this AC plasma display panel, a high emission efficiency can be obtained. Also described is another AC plasma display panel in which a data electrode having a large width part around the surface discharging gap and a narrow width part. The data electrode may further include a medium width part. In this AC plasma display panel, since counter discharge always occurs near a discharge gap of a scanning electrode by employing the data electrode having a specified shape, a high resolution panel with full-color display can be realized.
    Type: Grant
    Filed: September 21, 1999
    Date of Patent: November 12, 2002
    Assignee: NEC Corporation
    Inventor: Keiji Nunomura
  • Patent number: 6450850
    Abstract: In a display panel manufacturing method and a display device manufactured by the method, a plate-shaped partition wall-forming member is sandwiched between a mold having an inverted shape to partition walls and a support mold to press-mold the partition wall-forming member therebetween, thereby forming a partition wall member comprising partition wall portions and a bottom insulating layer portion while coming into close contact with the mold. Thereafter, the partition wall member is transferred onto a display substrate to complete a display panel.
    Type: Grant
    Filed: January 19, 2000
    Date of Patent: September 17, 2002
    Assignee: NEC Corporation
    Inventor: Keiji Nunomura
  • Publication number: 20020024303
    Abstract: Ribs for defining pixel cells are formed in the shape of a lattice, and sustain electrodes and scan electrodes are disposed near the ribs. The electrodes are spaced apart in each pixel cell, and the sustain electrode and the scan electrode are each cut away between pixel cells arranged in the row direction to provide each pixel cell with individually separated electrodes. In addition, between pixel cells adjacent to each other in the row direction, the sustain electrodes and the scan electrodes are connected to each other by means of a sustain-side bus electrode and a scan-side bus electrode, respectively. This makes it possible to provide a high luminous efficiency. Furthermore, each pixel cell is provided with a wide distance between the electrodes and thereby with a large effective opening portion. Thus, this provides only a small amount of reduction in intensity when the electrodes are spaced apart between the pixel cells arranged in the row direction in order to increase the luminous efficiency.
    Type: Application
    Filed: July 23, 2001
    Publication date: February 28, 2002
    Applicant: NEC CORPORATION
    Inventors: Yoshio Sano, Nobumitsu Aibara, Yoshiaki Yanai, Toshiyuki Akiyama, Tetsumasa Okamoto, Kazuaki Yanagida, Hirokazu Tateno, Naoto Hirano, Yoshito Tanaka, Tadashi Nakamura, Keiji Nunomura
  • Patent number: 6348762
    Abstract: A surface discharge type color plasma display panel (PDP) having high color temperature and small white color deviation. The plasma display panel comprises: a plurality of discharge electrode pairs each of which includes a scanning electrode and a retaining electrode and each of which form a surface discharge gap between the scanning electrode and the retaining electrode; a plurality of data electrodes disposed perpendicular to the surface discharge gap; and a plurality of display cells each defined at an area including an intersection between the data electrode and the discharge electrode pair, the plurality of display cells being grouped into a plurality of sets of display cells, each set including display cells for three primary colors.
    Type: Grant
    Filed: October 15, 1999
    Date of Patent: February 19, 2002
    Assignee: NEC Corporation
    Inventors: Keiji Nunomura, Kazuaki Yanagida
  • Patent number: 6342873
    Abstract: In a surface discharge type plasma display device, lead-out wirings for a plurality of surface discharge electrode pairs of a scanning electrode 3 and sustaining electrodes 4 are arranged such that current flowing directions of adjacent pairs of the surface discharge electrodes during a sustaining discharge period are opposite to each other.
    Type: Grant
    Filed: December 23, 1997
    Date of Patent: January 29, 2002
    Assignee: NEC Corporation
    Inventors: Mitsuo Ueoka, Keiji Nunomura
  • Publication number: 20010005189
    Abstract: First and second substrates are disposed oppositely to each other in a plasma display panel. A parallel-crossed partition wall, a plurality of bus electrodes, a plurality of display discharge electrodes, and a plurality of data electrodes are provided to the panel. The parallel-crossed partition wall defines a space between the first and second substrates into a plurality of display cells. The bus electrodes are provided in a side of the first substrate opposite the second substrate, and superposed on a portion of the partition wall extended in the line direction when seen from a plane. The display discharge electrodes each are extended from each of the bus electrodes in each of the display cells defined in the columnar direction by a portion of the partition wall overlapping with the bus electrode when seen from the plane. The data electrodes are provided in a side of the second substrate opposite the first substrate and extended in the columnar direction.
    Type: Application
    Filed: December 20, 2000
    Publication date: June 28, 2001
    Inventor: Keiji Nunomura
  • Patent number: 6052112
    Abstract: A sub-field array is formed by providing a sub-field corresponding to an m-th bit sub-field (m and n being a positive integers of m.ltoreq.n and representing the most significant bit place when m is 1) bit substantially at the center of the time axis of all the sub-field periods, and providing the other sub-fields than the m-th significant one on the opposite sides of and substantially in line symmetry with respect to the m-th significant bit sub-field. Less significant bit sub-fields are provided on the opposite sides of the close proximity of the central sub-field in the field period, and the odd and even order sub-fields are arranged in opposite sequences from one another. As the symmetrical arrangement sub-fields, odd and even scan line sub-fields are provided on the opposite sides of the central sub-field.
    Type: Grant
    Filed: October 23, 1997
    Date of Patent: April 18, 2000
    Assignee: NEC Corporation
    Inventors: Akira Tanaka, Keiji Nunomura
  • Patent number: 5957743
    Abstract: In a substrate manufacturing process for color plasma displays, it is made possible to form a phosphor coat in a desirable form all over a panel by introducing a step to coat the whole surface of a luminescent display section with a paste containing white particulates of titanium oxide or the like, which are finer than phosphor powder, after barriers are formed on a back substrate and before the discharge cell inside is sequentially coated with phosphors for different colors to make up luminescent pixels. By applying the particulate paste to the unfired barrier portion, which is then in a very porous state, before the phosphor coating stage, collective firing of the barriers and the phosphor layers is made possible.
    Type: Grant
    Filed: October 21, 1997
    Date of Patent: September 28, 1999
    Assignee: NEC Corporation
    Inventors: Tsuneo Konishi, Keiji Nunomura
  • Patent number: 5162701
    Abstract: A plasma display includes discharge gas spaces, first and second insulating substrates, stripe row electrodes, an insulating layer, a protective layer, stripe column electrodes, another insulating layer, phosphors, and ribs. The discharge gas spaces constitute a plurality of pixels. The first and second insulating substrates are arranged parallel to each other so as to sandwich the discharge gas spaces. The row electrodes are arranged on a surface of the first insulating substrate which opposes the discharge gas spaces. The first insluating layer is stacked on the stripe row electrodes. The protective layer is stacked on the insulating layer. The column electrodes are arranged on a surface of the second insulating substrate, which opposes the discharge gas spaces, in a direction perpendicular to the row electrodes. The second insulating layer is stacked on the column electrodes. The phosphors are stacked on the insulating layer at positions corresponding to the pixels, respectively.
    Type: Grant
    Filed: October 16, 1991
    Date of Patent: November 10, 1992
    Assignee: NEC Corporation
    Inventors: Yoshio Sano, Keiji Nunomura
  • Patent number: 5107182
    Abstract: A plasma display includes discharge gas spaces, first and second insulating substrates, stripe row electrodes, an insulating layer, a protective layer, stripe column electrodes, another insulating layer, phosphors, and ribs. The discharge gas spaces constitute a plurality of pixels. The first and second insulating substrates are arranged parallel to each other so as to sandwich the discharge gas spaces. The row electrodes are arranged on a surface of the first insulating substrate which opposes the discharge gas spaces. The first insulating layer is stacked on the stripe row electrodes. The protective layer is stacked on the insulating layer. The column electrodes are arranged on a surface of the second insulating substrate, which opposes the discharge gas spaces, in a direction perpendicular to the row electrodes. The second insulating layer is stacked on the column electrodes. The phosphors are stacked on the insulating layer at positions corresponding to the pixels, respectively.
    Type: Grant
    Filed: April 23, 1990
    Date of Patent: April 21, 1992
    Assignee: NEC Corporation
    Inventors: Yoshio Sano, Keiji Nunomura