Patents by Inventor Keiji Saeki

Keiji Saeki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5813115
    Abstract: When a semiconductor chip is mounted on a wiring substrate, an end of a metallic wire fed through a capillary is first fused to form a ball, which is in turn pressed against and bonded to an electrode pad formed on a semiconductor chip. The metallic wire is then cut at a location in the proximity of the ball so that a portion of the metallic wire remains as a protruding contact on the ball. The protruding contact is pressed against a shaping platform coated with a paste-like electrically-conductive adhesive film to thereby cause the protruding contact to have a given height and transfer a portion of the adhesive film to the protruding contact. The protruding contact is eventually bonded to an electrically-conductive film formed on the wiring substrate via the transferred portion of the adhesive film.
    Type: Grant
    Filed: August 2, 1995
    Date of Patent: September 29, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshihiko Misawa, Koichi Morita, Keiji Saeki, Setsuo Horimoto
  • Patent number: 5744382
    Abstract: An electronic chip component includes an electrode formed on a wafer, a passivation film formed on the water, and an organic protective film covering an entire surface of exposed portions of the electrode and the passivation film. Such component is packed in a package including a carrier tape having therethrough a space for receiving the component with one end of such space open. A cover is applied to close the open end of the space after the component is inserted therein.
    Type: Grant
    Filed: August 27, 1996
    Date of Patent: April 28, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshifumi Kitayama, Kazuhiro Mori, Keiji Saeki, Takashi Akiguchi
  • Patent number: 5667129
    Abstract: An IC component mounting method includes sucking each of different types of IC components at a supply position to which the IC component having an electrode-provided face thereof to be bonded to a circuit board, recognizing an image of the IC component to detect a sucking position at which a sucking nozzle does not interfere with an electrode of the IC component, detecting a height of the sucking position, positioning the sucking nozzle at the sucking position while the position of the sucking nozzle in a vertical direction is controlled, sucking the IC component by a mounting head, recognizing a position of the IC component sucked by the mounting head, and recognizing a reference position of the circuit board or an IC component-mounting position thereof, and positioning the IC component at the IC component-mounting position of the circuit board and then mounting the IC component on the circuit board.
    Type: Grant
    Filed: May 1, 1995
    Date of Patent: September 16, 1997
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koichi Morita, Yoshihiko Misawa, Keiji Saeki, Akira Kabeshita, Nobuhisa Watanabe
  • Patent number: 5646439
    Abstract: An electronic chip component includes an electrode formed on a wafer, a passivation film formed on the wafer, and an organic protective film covering an entire surface of exposed portions of the electrode and the passivation film. A package for packing the component includes a carrier tape having therethrough a space for receiving the component with one end or side of the space opened, and a cover tape for closing the open end of the space after the component is stored in the space. A method for packing the component includes the steps of storing the component in the space of the carrier tape with one end of the space opened, and closing the open end of the space with the cover tape.
    Type: Grant
    Filed: August 27, 1996
    Date of Patent: July 8, 1997
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshifumi Kitayama, Kazuhiro Mori, Keiji Saeki, Takashi Akiguchi
  • Patent number: 5622590
    Abstract: The top surface of an insulating substrate is formed with a plurality of electrodes for bump connection, while the undersurface of the insulating substrate is formed with external terminals which are arranged in an array. On the insulating substrate is provided a semiconductor chip. The undersurface of the semiconductor chip is formed with bump electrodes. The electrodes for bump connection are electrically connected to the bump electrodes by means of a conductive adhesive. The space between the semiconductor chip and the insulating substrate is filled with a resin which integrates the above two and dissipates heat generated from the semiconductor chip.
    Type: Grant
    Filed: April 28, 1995
    Date of Patent: April 22, 1997
    Assignee: Matsushita Electronics Corporation
    Inventors: Yoshinobu Kunitomo, Makoto Nozu, Yasuyuki Sakashita, Masahide Tsukamoto, Seiichi Nakatani, Keiji Saeki, Yoshifumi Kitayama
  • Patent number: 5550408
    Abstract: The top surface of an insulating substrate is formed with a plurality of electrodes for bump connection, while the undersurface of the insulating substrate is formed with external terminals which are arranged in a matrix. On the insulating substrate is provided a semiconductor chip. The undersurface of the semiconductor chip is formed with bump electrodes. The electrodes for bump connection are electrically connected to the bump electrodes by means of a conductive adhesive. The space between the semiconductor chip and the insulating substrate is filled with a resin which integrates the above two and dissipates heat generated from the semiconductor chip.
    Type: Grant
    Filed: March 23, 1995
    Date of Patent: August 27, 1996
    Assignee: Matsushita Electronics Corporation
    Inventors: Yoshinobu Kunitomo, Makoto Nozu, Yasuyuki Sakashita, Masahide Tsukamoto, Seiichi Nakatani, Keiji Saeki, Yoshifumi Kitayama
  • Patent number: 5436503
    Abstract: The top surface of an insulating substrate is formed with a plurality of electrodes for bump connection, while the undersurface of the insulating substrate is formed with external terminals which are arranged in an array. On the insulating substrate is provided a semiconductor chip. The undersurface of the semiconductor chip is formed with bump electrodes. The electrodes for bump connection are electrically connected to the bump electrodes by means of a conductive adhesive. The space between the semiconductor chip and the insulating substrate is filled with a resin which integrates the above two and dissipates heat generated from the semiconductor chip.
    Type: Grant
    Filed: November 17, 1993
    Date of Patent: July 25, 1995
    Assignee: Matsushita Electronics Corporation
    Inventors: Yoshinobu Kunitomo, Makoto Nozu, Yasuyuki Sakashita, Masahide Tsukamoto, Seiichi Nakatani, Keiji Saeki, Yoshifumi Kitayama
  • Patent number: 5240170
    Abstract: A method for bonding leads of an IC component with electrodes of a circuit board includes the steps of using a mounting device to hold the IC component with flat portions of the leads inclined downward, mounting the IC component on the circuit board at a predetermined position thereof with the IC component held by the mounting device, moving the mounting device toward the circuit board to compress the IC component against the circuit board at the predetermined position while allowing the leads to flex to accommodate for nonuniformity in the heights of metal pieces to be bonded with the electrodes and bending of the circuit board. In this manner, the flat portions of the leads are brought into close contact with the electrodes. The leads are then irradiated with an optical beam so as to melt the metal pieces of the electrodes for bonding of the leads to the circuit board.
    Type: Grant
    Filed: June 5, 1992
    Date of Patent: August 31, 1993
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazuto Nishida, Kazuhiro Nobori, Yoshifumi Kitayama, Keiji Saeki
  • Patent number: 4824010
    Abstract: At least one chip type component is soldered to a printed circuit board by independent first and second nozzles which spout molten solder so as to form respective first and second solder waves, with the printed circuit board sequentially passed through the first and second nozzles. The first and second solder waves define therebetween a space and flow at least in a direction of movement of the printed circuit board and in a direction counter to the direction of movement of the printed circuit board, respectively. The second nozzle is disposed at a level higher than the first nozzle such that the printed circuit board is moved obliquely upwardly.
    Type: Grant
    Filed: October 17, 1986
    Date of Patent: April 25, 1989
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takao Inoue, Keiji Saeki, Chuichi Matsuda, Schuichi Murakami
  • Patent number: 4743465
    Abstract: A method and apparatus for drawing a thick film circuit on a substrate by discharging a paste from a tank with a discharge hole. A waste drawing is performed by extruding the paste from the tank on a waste drawing section at a predetermined interval of non-drawing duration, thereby preventing paste clogging at the discharge hole and resulting in increase on workability and productivity.
    Type: Grant
    Filed: February 12, 1986
    Date of Patent: May 10, 1988
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Keiji Saeki, Shinichi Kudo, Hachiro Nakatsuji
  • Patent number: 4692351
    Abstract: A method and apparatus for drawing a thick film circuit on a substrate (2) by discharging a paste from a paste discharge hole provided at one end of a drawing nozzle (1), the drawing nozzle (1) being located close to the substrate (2) and relatively moved with respect to the substrate (2). The discharge rate of the paste is controlled in accordance with the relatively moving speed between the drawing nozzle (1) and the substrate (2), thereby preventing variations of film thickness and line width caused by variations in the moving speed and making it possible to form a thick film circuit at a high speed and with high accuracy.
    Type: Grant
    Filed: December 16, 1985
    Date of Patent: September 8, 1987
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yukio Maeda, Shinichi Kudo, Keiji Saeki
  • Patent number: 4425209
    Abstract: A photosetting resin composition containing more than 10% by weight of one or more resins each having more than 3 functional groups--acryloyl or methacryloyl radicals--and a sensitizer. Since the compositions contain more than 10% by weight of one or more resins each having more than three functional groups, they exhibit very satisfactory and well balanced resistance-to-solder (JISC-6481, 260.degree. C., 10 sec), flexural strength (JISP-8115, 0.38R, 180.degree. bending) and adhesion (JISD-0202, chequer pattern test).
    Type: Grant
    Filed: September 21, 1982
    Date of Patent: January 10, 1984
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Keiji Saeki, Junji Ikeda, Wakahata Tamotsu