Patents by Inventor Keiji Shuto

Keiji Shuto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Nonvolatile semiconductor memory device including NAND-type flash memory and the like
    Patent number: 8139407
    Abstract: A nonvolatile semiconductor memory device is provided with a memory cell array, a judgment potential correction circuit, and a readout circuit. In the memory cell array, a plurality of memory cells are arranged in a matrix form, and the array includes a first memory cell as a readout object and a second memory cell disposed adjacent to the first memory cell. The judgment potential correction circuit corrects a judgment potential based on a threshold value of the second memory cell. The readout circuit reads the first memory cell as the readout object by use of the corrected judgment potential.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: March 20, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsuhiro Sato, Keiji Shuto, Fumitaka Arai
  • NONVOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING NAND-TYPE FLASH MEMORY AND THE LIKE
    Publication number: 20110069542
    Abstract: A nonvolatile semiconductor memory device is provided with a memory cell array, a judgment potential correction circuit, and a readout circuit. In the memory cell array, a plurality of memory cells are arranged in a matrix form, and the array includes a first memory cell as a readout object and a second memory cell disposed adjacent to the first memory cell. The judgment potential correction circuit corrects a judgment potential based on a threshold value of the second memory cell. The readout circuit reads the first memory cell as the readout object by use of the corrected judgment potential.
    Type: Application
    Filed: November 29, 2010
    Publication date: March 24, 2011
    Inventors: Atsuhiro SATO, Keiji Shuto, Fumitaka Arai
  • Nonvolatile semiconductor memory device including NAND-type flash memory and the like
    Patent number: 7859898
    Abstract: A nonvolatile semiconductor memory device is provided with a memory cell array, a judgment potential correction circuit, and a readout circuit. In the memory cell array, a plurality of memory cells are arranged in a matrix form, and the array includes a first memory cell as a readout object and a second memory cell disposed adjacent to the first memory cell. The judgment potential correction circuit corrects a judgment potential based on a threshold value of the second memory cell. The readout circuit reads the first memory cell as the readout object by use of the corrected judgment potential.
    Type: Grant
    Filed: January 16, 2009
    Date of Patent: December 28, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsuhiro Sato, Keiji Shuto, Fumitaka Arai
  • NONVOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING NAND-TYPE FLASH MEMORY AND THE LIKE
    Publication number: 20090129158
    Abstract: A nonvolatile semiconductor memory device is provided with a memory cell array, a judgment potential correction circuit, and a readout circuit. In the memory cell array, a plurality of memory cells are arranged in a matrix form, and the array includes a first memory cell as a readout object and a second memory cell disposed adjacent to the first memory cell. The judgment potential correction circuit corrects a judgment potential based on a threshold value of the second memory cell. The readout circuit reads the first memory cell as the readout object by use of the corrected judgment potential.
    Type: Application
    Filed: January 16, 2009
    Publication date: May 21, 2009
    Inventors: Atsuhiro SATO, Keiji Shuto, Fumitaka Arai
  • Nonvolatile semiconductor memory device capable of controlling proximity effect due to coupling between adjacent charge storage layers
    Patent number: 7505312
    Abstract: There is disclosed a semiconductor integrated circuit device including a memory cell array having a plurality of blocks, a first non-volatile semiconductor memory cell which is arranged in the memory cell array and has an electric charge storage layer, and a second non-volatile semiconductor memory cell which is arranged in the memory cell array to be adjacent to the first non-volatile semiconductor memory cell and has an electric charge storage layer. Regular data writing is performed with respect to the second non-volatile semiconductor memory cell after regular data writing is carried out with respect to the first non-volatile semiconductor memory cell. Additional data writing is performed with respect to the first non-volatile semiconductor memory cell after regular data writing is carried out with respect to the second non-volatile semiconductor memory cell.
    Type: Grant
    Filed: June 7, 2006
    Date of Patent: March 17, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiko Matsunaga, Fumitaka Arai, Atsuhiro Sato, Makoto Sakuma, Masato Endo, Kiyohito Nishihara, Keiji Shuto, Naohisa Iino
  • Semiconductor integrated circuit device
    Publication number: 20070177431
    Abstract: There is disclosed a semiconductor integrated circuit device including a memory cell array having a plurality of blocks, a first non-volatile semiconductor memory cell which is arranged in the memory cell array and has an electric charge storage layer, and a second non-volatile semiconductor memory cell which is arranged in the memory cell array to be adjacent to the first non-volatile semiconductor memory cell and has an electric charge storage layer. Regular data writing is performed with respect to the second non-volatile semiconductor memory cell after regular data writing is carried out with respect to the first non-volatile semiconductor memory cell. Additional data writing is performed with respect to the first non-volatile semiconductor memory cell after regular data writing is carried out with respect to the second non-volatile semiconductor memory cell.
    Type: Application
    Filed: June 7, 2006
    Publication date: August 2, 2007
    Inventors: Yasuhiko Matsunaga, Fumitaka Arai, Atsuhiro Sato, Makoto Sakuma, Masato Endo, Kiyohito Nishihara, Keiji Shuto, Naohisa Iino
  • Nonvolatile semiconductor memory device including nand-type flash memory and the like
    Publication number: 20070159881
    Abstract: A nonvolatile semiconductor memory device is provided with a memory cell array, a judgment potential correction circuit, and a readout circuit. In the memory cell array, a plurality of memory cells are arranged in a matrix form, and the array includes a first memory cell as a readout object and a second memory cell disposed adjacent to the first memory cell. The judgment potential correction circuit corrects a judgment potential based on a threshold value of the second memory cell. The readout circuit reads the first memory cell as the readout object by use of the corrected judgment potential.
    Type: Application
    Filed: June 26, 2006
    Publication date: July 12, 2007
    Inventors: Atsuhiro Sato, Keiji Shuto, Fumitaka Arai