Patents by Inventor Keiji Takai

Keiji Takai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8258608
    Abstract: In a lead frame used for manufacturing a semiconductor device by forming a circuit pattern group including unit lead frames having plural upper side terminal parts in the periphery of a semiconductor element mounting region in one line or plural lines and an outer frame surrounding the circuit pattern group in a state of having a gap in a lead frame material and then mounting a semiconductor element every the unit lead frame and carrying out necessary wiring and enclosing the entire surface of the circuit pattern group in which the semiconductor element is mounted and a part of the outer frame with a resin from an upper surface side and further etching from a lower surface side and forming lower side terminal parts joined to the upper side terminal parts of the circuit pattern group, the circuit pattern group and the outer frame are had and the inner edge of the outer frame is formed in an uneven portion in plan view and bonding between the resin and the outer frame is enhanced.
    Type: Grant
    Filed: October 25, 2010
    Date of Patent: September 4, 2012
    Assignee: Mitsui High-Tec, Inc.
    Inventor: Keiji Takai
  • Patent number: 8003444
    Abstract: A method of manufacturing a semiconductor device 28 in which a plating mask 38, 39 having a noble metal plating layer 35 as an uppermost layer is formed at a predetermined portion on an obverse surface side or a reverse surface side of a leadframe material 10, and the leadframe material 10 is consecutively subjected to etching by using the plating mask 38, 39 as a resist mask, so as to form external connection terminal portions 22 which electrically communicate with a semiconductor element 18 disposed in an interior of an encapsulating resin 21, and which project downwardly. Base metal plating or noble metal plating 33 exhibiting etching solution resistance is provided as a lowermost layer of the plating mask 38, 39.
    Type: Grant
    Filed: August 9, 2006
    Date of Patent: August 23, 2011
    Assignee: Mitsui High-Tec, Inc.
    Inventors: Keiji Takai, Tetsuyuki Hirashima
  • Publication number: 20110095405
    Abstract: In a lead frame used for manufacturing a semiconductor device by forming a circuit pattern group including unit lead frames having plural upper side terminal parts in the periphery of a semiconductor element mounting region in one line or plural lines and an outer frame surrounding the circuit pattern group in a state of having a gap in a lead frame material and then mounting a semiconductor element every the unit lead frame and carrying out necessary wiring and enclosing the entire surface of the circuit pattern group in which the semiconductor element is mounted and a part of the outer frame with a resin from an upper surface side and further etching from a lower surface side and forming lower side terminal parts joined to the upper side terminal parts of the circuit pattern group, the circuit pattern group and the outer frame are had and the inner edge of the outer frame is formed in an uneven portion in plan view and bonding between the resin and the outer frame is enhanced.
    Type: Application
    Filed: October 25, 2010
    Publication date: April 28, 2011
    Applicant: MITSUI HIGH-TECH, INC.
    Inventor: Keiji TAKAI
  • Publication number: 20070181983
    Abstract: A method of manufacturing a semiconductor device 28 in which a plating mask 38, 39 having a noble metal plating layer 35 as an uppermost layer is formed at a predetermined portion on an obverse surface side or a reverse surface side of a leadframe material 10, and the leadframe material 10 is consecutively subjected to etching by using the plating mask 38, 39 as a resist mask, so as to form external connection terminal portions 22 which electrically communicate with a semiconductor element 18 disposed in an interior of an encapsulating resin 21, and which project downwardly. Base metal plating or noble metal plating 33 exhibiting etching solution resistance is provided as a lowermost layer of the plating mask 38, 39.
    Type: Application
    Filed: August 9, 2006
    Publication date: August 9, 2007
    Inventors: Keiji Takai, Tetsuyuki Hirashima
  • Patent number: 6659385
    Abstract: A wire-winding machine for forming coils (20) on individual magnetic pole teeth (11a) of a core member (13) which is produced by joining a plurality of core segments (11), each of the core segments (11) having a yoke portion (11c) and a magnetic pole tooth (11a) projectingly formed on an inside surface (11d) of the yoke portion (11c), comprises a core member positioner including a rotating roller (14), large-diameter guide rollers (21) and small-diameter guide rollers (22) which together serve to bend the core member (13) and hold it in a position where the core segments (11.3, 11.5) adjacent to the core segment (11.4) on which the coil (20) is currently wound do not project in the direction of its magnetic pole tooth (11a) beyond a boundary surface (S) of the yoke portion (11c) of the core segment (11.4) on which the coil (20) is currently wound.
    Type: Grant
    Filed: August 7, 2001
    Date of Patent: December 9, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiroyuki Akita, Yuji Nakahara, Nobuaki Miyake, Kazuya Omura, Keiji Takai, Kazunari Tomita, Naoki Kawasugi
  • Publication number: 20020050541
    Abstract: A wire-winding machine for forming coils (20) on individual magnetic pole teeth (11a) of a core member (13) which is produced by joining a plurality of core segments (11), each of the core segments (11) having a yoke portion (11c) and a magnetic pole tooth (11a) projectingly formed on an inside surface (11d) of the yoke portion (11c), comprises a core member positioner including a rotating roller (14), large-diameter guide rollers (21) and small-diameter guide rollers (22) which together serve to bend the core member (13) and hold it in a position where the core segments (11.3, 11.5) adjacent to the core segment (11.4) on which the coil (20) is currently wound do not project in the direction of its magnetic pole tooth (11a) beyond a boundary surface (S) of the yoke portion (11c) of the core segment (11.4) on which the coil (20) is currently wound.
    Type: Application
    Filed: August 7, 2001
    Publication date: May 2, 2002
    Inventors: Hiroyuki Akita, Yuji Nakahara, Nobuaki Miyake, Kazuya Omura, Keiji Takai, Kazunari Tomita, Naoki Kawasugi
  • Patent number: 5717252
    Abstract: A semiconductor device which remains highly reliable and is easy to mount even when a bonding pad pitch is reduced. The semiconductor device is featured in that a thermally conductive support substrate in which a semiconductor chip is fixed to a recessed portion is mounted on the reverse side of an insulating tape, that is, a TAB substrate having a conductor pattern on the surface; and solder balls are placed on the front side of the insulating tape to ensure connection to the conductor pattern on the front side through holes.
    Type: Grant
    Filed: December 2, 1996
    Date of Patent: February 10, 1998
    Assignee: Mitsui High-tec, Inc.
    Inventors: Takashi Nakashima, Atsushi Fukui, Keiji Takai, Koji Tateishi
  • Patent number: 5661086
    Abstract: Method for producing semiconductor devices comprises a first step in which a plurality of metal substrates each of which is provided with a die mounting region at a central portion thereof are connected in series to produce a train of connected metal substrates by means of first connecting tabs and a pair of first side rails each of which is provided with first positioning pilot apertures are connected to the train by means of second connecting tabs to produce a metal substrate frame, a second step in which a plurality of circuit substrates each of which is provided with a lead pattern around an opening formed at the central portion thereof are connected in series by means of third connecting tabs to produce a train of connected circuit substrates and a pair of second side rails each of which is provided with second positioning pilot apertures are connected by fourth connecting tabs to produce a circuit substrate frame, a third step in which both frames are alinged with each other making use of the first and
    Type: Grant
    Filed: January 11, 1996
    Date of Patent: August 26, 1997
    Assignee: Mitsui High-Tec, Inc.
    Inventors: Takashi Nakashima, Keiji Takai, Kouji Tateishi
  • Patent number: 5614443
    Abstract: Method of producing a frame made of connected semiconductor die mounting substrates comprises i) a first step for producing a metal substrate sheet wherein an original material for metal substrate sheet of a desired size is cut out from a metal material and an erosion preventing layer is provided on the entire surface thereof, ii) a second step for producing a circuit substrate sheet wherein the circuit substrate sheet is made of a resin substrate coated with a copper leaf layer and is provided with a lead pattern on the surface thereof in place, iii) a third step for producing a connected semiconductor die mounting substrate sheet by adhering the metal substrate sheet to the circuit substrate sheet, iv) a fourth step for forming a plurality of pilot apertures and slits on the connected semiconductor die mounting substrate sheet by press working and v) a fifth step for producing a plurality of connected semiconductor die mounting substrate frames by separating the connected semiconductor die mounting substrat
    Type: Grant
    Filed: March 27, 1996
    Date of Patent: March 25, 1997
    Assignee: Mitsui High-tec, Inc.
    Inventors: Takashi Nakashima, Keiji Takai, Kouji Tateishi
  • Patent number: 4477447
    Abstract: This invention relates to novel 7-acylaminocephalosporanic acid derivatives of high antimicrobial activity, to processes for their preparation, and to pharmaceutical compositions comprising said derivatives, said derivatives being of the formula: ##STR1## wherein R.sup.1 is amino or protected amino,R.sup.2 is dialkanoyloxy(lower)alkyl; alkyl having one or more substituents selected from the group consisting of hydroxy, protected hydroxy, alkoxy, carboxy, protected carboxy, cycloalkylcarbonyloxy and heterocyclic group; lower alkoxycarbonyloxy(lower)alkyl; azido(lower)alkoxycarbonyloxy(lower)alkyl; aroyloxy(lower)alkyl; higher alkanoyloxy(lower)alkyl; phthalidyl; or phthalidylidene(lower)alkyl,R.sup.3 is lower alkyl,Y is thio (--S--) or sulfinyl (--S--), and the dotted line represents 2- or 3-cephem nuclei.
    Type: Grant
    Filed: February 24, 1982
    Date of Patent: October 16, 1984
    Assignee: Fujisawa Pharmaceutical Co., Ltd.
    Inventors: Ikuo Ueda, Tsutomu Teraji, Takao Takaya, Keiji Takai, Hisashi Takasugi, Fumio Shimojo, Shigetaka Nishino