Patents by Inventor Keiji Tatani
Keiji Tatani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240096925Abstract: A semiconductor device including a first semiconductor section including a first wiring layer at one side thereof, the first semiconductor section further including a photodiode, a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together, a third semiconductor section including a third wiring layer at one side thereof, the second and the third semiconductor sections being secured together such the first semiconductor section, second semiconductor section, and the third semiconductor section are stacked together, and a first conductive material electrically connecting at least two of (i) the first wiring layer, (ii) the second wiring layer, and (iii) the third wiring layer such that the electrically connected wiring layers are in electrical communication.Type: ApplicationFiled: November 27, 2023Publication date: March 21, 2024Applicant: SONY GROUP CORPORATIONInventors: Taku UMEBAYASHI, Keiji TATANI, Hajime INOUE, Ryuichi KANAMURA
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Patent number: 11875989Abstract: A semiconductor device including a first semiconductor section including a first wiring layer at one side thereof, the first semiconductor section further including a photodiode, a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together, a third semiconductor section including a third wiring layer at one side thereof, the second and the third semiconductor sections being secured together such the first semiconductor section, second semiconductor section, and the third semiconductor section are stacked together, and a first conductive material electrically connecting at least two of (i) the first wiring layer, (ii) the second wiring layer, and (iii) the third wiring layer such that the electrically connected wiring layers are in electrical communication.Type: GrantFiled: April 13, 2022Date of Patent: January 16, 2024Assignee: SONY GROUP CORPORATIONInventors: Taku Umebayashi, Keiji Tatani, Hajime Inoue, Ryuichi Kanamura
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Patent number: 11626432Abstract: The present disclosure relates to a solid-state imaging device and an electronic device that are configured to suppress the occurrence of noise and white blemishes in an amplification transistor having an element separation region which is formed by ion implantation. An amplification transistor has an element separation region formed by ion implantation. A channel region insulating film which is at least a part of a gate insulating film above a channel region of the amplification transistor is thin compared to a gate insulating film of a selection transistor, and an element separation region insulating film which is at least a part of a gate insulating film above the element separation region of the amplification transistor is thick compared to the channel region insulating film. The present disclosure can be applied to, for example, a CMOS image sensor, etc.Type: GrantFiled: July 3, 2019Date of Patent: April 11, 2023Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Yusuke Otake, Toshifumi Wakano, Takuya Sano, Yusuke Tanaka, Keiji Tatani, Hideo Harifuchi, Eiichi Tauchi, Hiroki Iwashita, Akira Matsumoto
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Publication number: 20220246668Abstract: A semiconductor device including a first semiconductor section including a first wiring layer at one side thereof, the first semiconductor section further including a photodiode, a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together, a third semiconductor section including a third wiring layer at one side thereof, the second and the third semiconductor sections being secured together such the first semiconductor section, second semiconductor section, and the third semiconductor section are stacked together, and a first conductive material electrically connecting at least two of (i) the first wiring layer, (ii) the second wiring layer, and (iii) the third wiring layer such that the electrically connected wiring layers are in electrical communication.Type: ApplicationFiled: April 13, 2022Publication date: August 4, 2022Applicant: SONY GROUP CORPORATIONInventors: Taku UMEBAYASHI, Keiji TATANI, Hajime INOUE, Ryuichi KANAMURA
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Patent number: 11374049Abstract: A semiconductor device including a first semiconductor section including a first wiring layer at one side thereof, the first semiconductor section further including a photodiode, a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together, a third semiconductor section including a third wiring layer at one side thereof, the second and the third semiconductor sections being secured together such the first semiconductor section, second semiconductor section, and the third semiconductor section are stacked together, and a first conductive material electrically connecting at least two of (i) the first wiring layer, (ii) the second wiring layer, and (iii) the third wiring layer such that the electrically connected wiring layers are in electrical communication.Type: GrantFiled: October 12, 2020Date of Patent: June 28, 2022Assignee: SONY CORPORATIONInventors: Taku Umebayashi, Keiji Tatani, Hajime Inoue, Ryuichi Kanamura
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Patent number: 11355533Abstract: A solid-state imaging device includes a photoelectric conversion section which is disposed on a semiconductor substrate and which photoelectrically converts incident light into signal charges, a pixel transistor section which is disposed on the semiconductor substrate and which converts signal charges read out from the photoelectric conversion section into a voltage, and an element isolation region which is disposed on the semiconductor substrate and which isolates the photoelectric conversion section from an active region in which the pixel transistor section is disposed. The pixel transistor section includes a plurality of transistors. Among the plurality of transistors, in at least one transistor in which the gate width direction of its gate electrode is oriented toward the photoelectric conversion section, at least a photoelectric conversion section side portion of the gate electrode is disposed within and on the active region with a gate insulating film therebetween.Type: GrantFiled: July 10, 2017Date of Patent: June 7, 2022Assignee: SONY CORPORATIONInventors: Takuji Matsumoto, Keiji Tatani, Tetsuji Yamaguchi, Masashi Nakata
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Patent number: 11175754Abstract: The present invention provides an electronic apparatus and an information processing method that allow a user who uses a writing tool to perform write actions such as writing a letter and drawing a picture to learn and improve skills while being highly motivated and having fun. An electronic apparatus according to an embodiment of the present disclosure includes: a pen-type main body having a writing function or a main body attachable to a writing tool; a detection part provided in the main body for detecting frequency of a writing action of a user; a storage part for storing data including at least any of image data and numeric data; and a control part that performs control to select image data or numeric data from the storage part corresponding to the frequency detected by the detection part and to display an image based on the selected image data or numeric data on a display part.Type: GrantFiled: March 12, 2018Date of Patent: November 16, 2021Inventor: Keiji Tatani
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Publication number: 20210351213Abstract: A solid-state imaging device includes a first-conductivity-type semiconductor well region, a plurality of pixels each of which is formed on the semiconductor well region and is composed of a photoelectric conversion portion and a pixel transistor, an element isolation region provided between the pixels and in the pixels, and an element isolation region being free from an insulation film and being provided between desired pixel transistors.Type: ApplicationFiled: July 22, 2021Publication date: November 11, 2021Applicant: Sony Group CorporationInventors: Keiji Tatani, Fumihiko Koga, Takashi Nagano
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Patent number: 11127771Abstract: Solid-state imaging devices, methods of producing a solid-state imaging device, and electronic apparatuses are provided. More particularly, a solid-state image device includes a silicon substrate, and at least a first photodiode formed in the silicon substrate. The device also includes an epitaxial layer with a first surface adjacent a surface of the silicon substrate, and a transfer transistor with a gate electrode that extends from the at least a first photodiode to a second surface of the epitaxial layer opposite the first surface. In further embodiments, a solid-state imaging device with a plurality of pixels formed in a second semiconductor substrate wherein the pixels are symmetrical with respect to a center point is provided. A floating diffusion is formed in an epitaxial layer, and a plurality of transfer gate electrodes that are each electrically connected to the floating diffusion by one of the transfer gate electrodes is provided.Type: GrantFiled: October 24, 2018Date of Patent: September 21, 2021Assignee: SONY CORPORATIONInventors: Yusuke Tanaka, Toshifumi Wakano, Keiji Tatani, Takashi Nagano, Hayato Iwamoto, Keiichi Nakazawa, Tomoyuki Hirano, Shinpei Yamaguchi, Shunsuke Maruyama
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Patent number: 11094725Abstract: Solid-state imaging devices, methods of producing a solid-state imaging device, and electronic apparatuses are provided. More particularly, a solid-state image device includes a silicon substrate, and at least a first photodiode formed in the silicon substrate. The device also includes an epitaxial layer with a first surface adjacent a surface of the silicon substrate, and a transfer transistor with a gate electrode that extends from the at least a first photodiode to a second surface of the epitaxial layer opposite the first surface. In further embodiments, a solid-state imaging device with a plurality of pixels formed in a second semiconductor substrate wherein the pixels are symmetrical with respect to a center point is provided. A floating diffusion is formed in an epitaxial layer, and a plurality of transfer gate electrodes that are each electrically connected to the floating diffusion by one of the transfer gate electrodes is provided.Type: GrantFiled: September 4, 2018Date of Patent: August 17, 2021Assignee: SONY CORPORATIONInventors: Yusuke Tanaka, Toshifumi Wakano, Keiji Tatani, Takashi Nagano, Hayato Iwamoto, Keiichi Nakazawa, Tomoyuki Hirano, Shinpei Yamaguchi, Shunsuke Maruyama
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Patent number: 11088187Abstract: A solid-state imaging device includes a first-conductivity-type semiconductor well region, a plurality of pixels each of which is formed on the semiconductor well region and is composed of a photoelectric conversion portion and a pixel transistor, an element isolation region provided between the pixels and in the pixels, and an element isolation region being free from an insulation film and being provided between desired pixel transistors.Type: GrantFiled: August 28, 2018Date of Patent: August 10, 2021Inventors: Keiji Tatani, Fumihiko Koga, Takashi Nagano
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Publication number: 20210132709Abstract: The present invention provides an electronic apparatus and an information processing method that allow a user who uses a writing tool to perform write actions such as writing a letter and drawing a picture to learn and improve skills while being highly motivated and having fun. An electronic apparatus according to an embodiment of the present disclosure includes: a pen-type main body having a writing function or a main body attachable to a writing tool; a detection part provided in the main body for detecting frequency of a writing action of a user; a storage part for storing data including at least any of image data and numeric data; and a control part that performs control to select image data or numeric data from the storage part corresponding to the frequency detected by the detection part and to display an image based on the selected image data or numeric data on a display part.Type: ApplicationFiled: March 12, 2018Publication date: May 6, 2021Inventor: Keiji Tatani
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Publication number: 20210043676Abstract: A semiconductor device including a first semiconductor section including a first wiring layer at one side thereof, the first semiconductor section further including a photodiode, a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together, a third semiconductor section including a third wiring layer at one side thereof, the second and the third semiconductor sections being secured together such the first semiconductor section, second semiconductor section, and the third semiconductor section are stacked together, and a first conductive material electrically connecting at least two of (i) the first wiring layer, (ii) the second wiring layer, and (iii) the third wiring layer such that the electrically connected wiring layers are in electrical communication.Type: ApplicationFiled: October 12, 2020Publication date: February 11, 2021Applicant: SONY CORPORATIONInventors: Taku UMEBAYASHI, Keiji TATANI, Hajime INOUE, Ryuichi KANAMURA
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Patent number: 10840290Abstract: A semiconductor device including a first semiconductor section including a first wiring layer at one side thereof, the first semiconductor section further including a photodiode, a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together, a third semiconductor section including a third wiring layer at one side thereof, the second and the third semiconductor sections being secured together such the first semiconductor section, second semiconductor section, and the third semiconductor section are stacked together, and a first conductive material electrically connecting at least two of (i) the first wiring layer, (ii) the second wiring layer, and (iii) the third wiring layer such that the electrically connected wiring layers are in electrical communication.Type: GrantFiled: August 29, 2019Date of Patent: November 17, 2020Assignee: Sony CorporationInventors: Taku Umebayashi, Keiji Tatani, Hajime Inoue, Ryuichi Kanamura
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Patent number: 10658405Abstract: The present disclosure relates to a solid-state image sensor, an electronic apparatus and an imaging method by which specific processing other than normal processing can be sped up with reduced power consumption. The solid-state image sensor includes a pixel outputting a pixel signal used to construct an image and a logic circuit driving the pixel, and is configured of a stacked structure in which a first semiconductor substrate including a plurality of the pixels and a second semiconductor substrate including the logic circuit are joined together. In addition, among the plurality of pixels, a specific pixel is connected to the logic circuit independently of a normal pixel, the specific pixel being the pixel that outputs the pixel signal used in the specific processing other than imaging processing in which the image is imaged. The present technology can be applied to a stacked solid-state image sensor, for example.Type: GrantFiled: December 7, 2018Date of Patent: May 19, 2020Assignee: Sony CorporationInventors: Keiji Tatani, Tomoharu Ogita, Takashi Nagano
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Publication number: 20200035744Abstract: A semiconductor device including a first semiconductor section including a first wiring layer at one side thereof, the first semiconductor section further including a photodiode, a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together, a third semiconductor section including a third wiring layer at one side thereof, the second and the third semiconductor sections being secured together such the first semiconductor section, second semiconductor section, and the third semiconductor section are stacked together, and a first conductive material electrically connecting at least two of (i) the first wiring layer, (ii) the second wiring layer, and (iii) the third wiring layer such that the electrically connected wiring layers are in electrical communication.Type: ApplicationFiled: August 29, 2019Publication date: January 30, 2020Applicant: SONY CORPORATIONInventors: Taku UMEBAYASHI, Keiji TATANI, Hajime INOUE, Ryuichi KANAMURA
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Patent number: 10535700Abstract: A semiconductor device including a first semiconductor section including a first wiring layer at one side thereof, the first semiconductor section further including a photodiode, a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together, a third semiconductor section including a third wiring layer at one side thereof, the second and the third semiconductor sections being secured together such the first semiconductor section, second semiconductor section, and the third semiconductor section are stacked together, and a first conductive material electrically connecting at least two of (i) the first wiring layer, (ii) the second wiring layer, and (iii) the third wiring layer such that the electrically connected wiring layers are in electrical communication.Type: GrantFiled: July 23, 2018Date of Patent: January 14, 2020Assignee: Sony CorporationInventors: Taku Umebayashi, Keiji Tatani, Hajime Inoue, Ryuichi Kanamura
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Patent number: 10475845Abstract: A semiconductor device including a first semiconductor section including a first wiring layer at one side thereof, the first semiconductor section further including a photodiode, a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together, a third semiconductor section including a third wiring layer at one side thereof, the second and the third semiconductor sections being secured together such the first semiconductor section, second semiconductor section, and the third semiconductor section are stacked together, and a first conductive material electrically connecting at least two of (i) the first wiring layer, (ii) the second wiring layer, and (iii) the third wiring layer such that the electrically connected wiring layers are in electrical communication.Type: GrantFiled: April 2, 2019Date of Patent: November 12, 2019Assignee: Sony CorporationInventors: Taku Umebayashi, Keiji Tatani, Hajime Inoue, Ryuichi Kanamura
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Publication number: 20190326338Abstract: The present disclosure relates to a solid-state imaging device and an electronic device that are configured to suppress the occurrence of noise and white blemishes in an amplification transistor having an element separation region which is formed by ion implantation. An amplification transistor has an element separation region formed by ion implantation. A channel region insulating film which is at least a part of a gate insulating film above a channel region of the amplification transistor is thin compared to a gate insulating film of a selection transistor, and an element separation region insulating film which is at least a part of a gate insulating film above the element separation region of the amplification transistor is thick compared to the channel region insulating film. The present disclosure can be applied to, for example, a CMOS image sensor, etc.Type: ApplicationFiled: July 3, 2019Publication date: October 24, 2019Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Yusuke OTAKE, Toshifumi WAKANO, Takuya SANO, Yusuke TANAKA, Keiji TATANI, Hideo HARIFUCHI, Eiichi TAUCHI, Hiroki IWASHITA, Akira MATSUMOTO
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Patent number: 10438983Abstract: Disclosed is a solid-state imaging device which includes a pixel section, a peripheral circuit section, a first isolation region formed with a STI structure on a semiconductor substrate in the peripheral circuit section, and a second isolation region formed with the STI structure on the semiconductor substrate in the pixel section. The portion of the second isolation region buried into the semiconductor substrate is shallower than the portion buried into the semiconductor substrate of the first isolation region, and the height of the upper face of the second isolation region is equal to that of the first isolation region. A method of producing the solid-state imaging device and an electronic device provided with the solid-state imaging devices are also disclosed.Type: GrantFiled: March 17, 2016Date of Patent: October 8, 2019Assignee: Sony CorporationInventors: Keiji Tatani, Takuji Matsumoto, Yasushi Tateshita, Fumihiko Koga, Takashi Nagano, Takahiro Toyoshima, Tetsuji Yamaguchi, Keiichi Nakazawa, Naoyuki Miyashita, Yoshihiko Nagahama