Patents by Inventor Keiji Tatani

Keiji Tatani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210132709
    Abstract: The present invention provides an electronic apparatus and an information processing method that allow a user who uses a writing tool to perform write actions such as writing a letter and drawing a picture to learn and improve skills while being highly motivated and having fun. An electronic apparatus according to an embodiment of the present disclosure includes: a pen-type main body having a writing function or a main body attachable to a writing tool; a detection part provided in the main body for detecting frequency of a writing action of a user; a storage part for storing data including at least any of image data and numeric data; and a control part that performs control to select image data or numeric data from the storage part corresponding to the frequency detected by the detection part and to display an image based on the selected image data or numeric data on a display part.
    Type: Application
    Filed: March 12, 2018
    Publication date: May 6, 2021
    Inventor: Keiji Tatani
  • Publication number: 20210043676
    Abstract: A semiconductor device including a first semiconductor section including a first wiring layer at one side thereof, the first semiconductor section further including a photodiode, a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together, a third semiconductor section including a third wiring layer at one side thereof, the second and the third semiconductor sections being secured together such the first semiconductor section, second semiconductor section, and the third semiconductor section are stacked together, and a first conductive material electrically connecting at least two of (i) the first wiring layer, (ii) the second wiring layer, and (iii) the third wiring layer such that the electrically connected wiring layers are in electrical communication.
    Type: Application
    Filed: October 12, 2020
    Publication date: February 11, 2021
    Applicant: SONY CORPORATION
    Inventors: Taku UMEBAYASHI, Keiji TATANI, Hajime INOUE, Ryuichi KANAMURA
  • Patent number: 10840290
    Abstract: A semiconductor device including a first semiconductor section including a first wiring layer at one side thereof, the first semiconductor section further including a photodiode, a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together, a third semiconductor section including a third wiring layer at one side thereof, the second and the third semiconductor sections being secured together such the first semiconductor section, second semiconductor section, and the third semiconductor section are stacked together, and a first conductive material electrically connecting at least two of (i) the first wiring layer, (ii) the second wiring layer, and (iii) the third wiring layer such that the electrically connected wiring layers are in electrical communication.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: November 17, 2020
    Assignee: Sony Corporation
    Inventors: Taku Umebayashi, Keiji Tatani, Hajime Inoue, Ryuichi Kanamura
  • Patent number: 10658405
    Abstract: The present disclosure relates to a solid-state image sensor, an electronic apparatus and an imaging method by which specific processing other than normal processing can be sped up with reduced power consumption. The solid-state image sensor includes a pixel outputting a pixel signal used to construct an image and a logic circuit driving the pixel, and is configured of a stacked structure in which a first semiconductor substrate including a plurality of the pixels and a second semiconductor substrate including the logic circuit are joined together. In addition, among the plurality of pixels, a specific pixel is connected to the logic circuit independently of a normal pixel, the specific pixel being the pixel that outputs the pixel signal used in the specific processing other than imaging processing in which the image is imaged. The present technology can be applied to a stacked solid-state image sensor, for example.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: May 19, 2020
    Assignee: Sony Corporation
    Inventors: Keiji Tatani, Tomoharu Ogita, Takashi Nagano
  • Publication number: 20200035744
    Abstract: A semiconductor device including a first semiconductor section including a first wiring layer at one side thereof, the first semiconductor section further including a photodiode, a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together, a third semiconductor section including a third wiring layer at one side thereof, the second and the third semiconductor sections being secured together such the first semiconductor section, second semiconductor section, and the third semiconductor section are stacked together, and a first conductive material electrically connecting at least two of (i) the first wiring layer, (ii) the second wiring layer, and (iii) the third wiring layer such that the electrically connected wiring layers are in electrical communication.
    Type: Application
    Filed: August 29, 2019
    Publication date: January 30, 2020
    Applicant: SONY CORPORATION
    Inventors: Taku UMEBAYASHI, Keiji TATANI, Hajime INOUE, Ryuichi KANAMURA
  • Patent number: 10535700
    Abstract: A semiconductor device including a first semiconductor section including a first wiring layer at one side thereof, the first semiconductor section further including a photodiode, a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together, a third semiconductor section including a third wiring layer at one side thereof, the second and the third semiconductor sections being secured together such the first semiconductor section, second semiconductor section, and the third semiconductor section are stacked together, and a first conductive material electrically connecting at least two of (i) the first wiring layer, (ii) the second wiring layer, and (iii) the third wiring layer such that the electrically connected wiring layers are in electrical communication.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: January 14, 2020
    Assignee: Sony Corporation
    Inventors: Taku Umebayashi, Keiji Tatani, Hajime Inoue, Ryuichi Kanamura
  • Patent number: 10475845
    Abstract: A semiconductor device including a first semiconductor section including a first wiring layer at one side thereof, the first semiconductor section further including a photodiode, a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together, a third semiconductor section including a third wiring layer at one side thereof, the second and the third semiconductor sections being secured together such the first semiconductor section, second semiconductor section, and the third semiconductor section are stacked together, and a first conductive material electrically connecting at least two of (i) the first wiring layer, (ii) the second wiring layer, and (iii) the third wiring layer such that the electrically connected wiring layers are in electrical communication.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: November 12, 2019
    Assignee: Sony Corporation
    Inventors: Taku Umebayashi, Keiji Tatani, Hajime Inoue, Ryuichi Kanamura
  • Publication number: 20190326338
    Abstract: The present disclosure relates to a solid-state imaging device and an electronic device that are configured to suppress the occurrence of noise and white blemishes in an amplification transistor having an element separation region which is formed by ion implantation. An amplification transistor has an element separation region formed by ion implantation. A channel region insulating film which is at least a part of a gate insulating film above a channel region of the amplification transistor is thin compared to a gate insulating film of a selection transistor, and an element separation region insulating film which is at least a part of a gate insulating film above the element separation region of the amplification transistor is thick compared to the channel region insulating film. The present disclosure can be applied to, for example, a CMOS image sensor, etc.
    Type: Application
    Filed: July 3, 2019
    Publication date: October 24, 2019
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Yusuke OTAKE, Toshifumi WAKANO, Takuya SANO, Yusuke TANAKA, Keiji TATANI, Hideo HARIFUCHI, Eiichi TAUCHI, Hiroki IWASHITA, Akira MATSUMOTO
  • Patent number: 10438983
    Abstract: Disclosed is a solid-state imaging device which includes a pixel section, a peripheral circuit section, a first isolation region formed with a STI structure on a semiconductor substrate in the peripheral circuit section, and a second isolation region formed with the STI structure on the semiconductor substrate in the pixel section. The portion of the second isolation region buried into the semiconductor substrate is shallower than the portion buried into the semiconductor substrate of the first isolation region, and the height of the upper face of the second isolation region is equal to that of the first isolation region. A method of producing the solid-state imaging device and an electronic device provided with the solid-state imaging devices are also disclosed.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: October 8, 2019
    Assignee: Sony Corporation
    Inventors: Keiji Tatani, Takuji Matsumoto, Yasushi Tateshita, Fumihiko Koga, Takashi Nagano, Takahiro Toyoshima, Tetsuji Yamaguchi, Keiichi Nakazawa, Naoyuki Miyashita, Yoshihiko Nagahama
  • Patent number: 10418397
    Abstract: A solid-state imaging device includes pixels each having a photoelectric conversion element for converting incident light to an electric signal, color filters associated with the pixels and having a plurality of color filter components, microlenses converging the incident light through the color filters to the photoelectric conversion elements, a light shielding film disposed between the color filter components of the color filters, and a nonplanarized adhesive film provided between the color filters and the light shielding film.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: September 17, 2019
    Assignee: Sony Corporation
    Inventors: Tomoharu Ogita, Atsushi Yamamoto, Keiji Tatani, Yoichi Ootsuka, Kiyotaka Tabuchi
  • Publication number: 20190229145
    Abstract: A semiconductor device including a first semiconductor section including a first wiring layer at one side thereof, the first semiconductor section further including a photodiode, a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together, a third semiconductor section including a third wiring layer at one side thereof, the second and the third semiconductor sections being secured together such the first semiconductor section, second semiconductor section, and the third semiconductor section are stacked together, and a first conductive material electrically connecting at least two of (i) the first wiring layer, (ii) the second wiring layer, and (iii) the third wiring layer such that the electrically connected wiring layers are in electrical communication.
    Type: Application
    Filed: April 2, 2019
    Publication date: July 25, 2019
    Applicant: SONY CORPORATION
    Inventors: Taku UMEBAYASHI, Keiji TATANI, Hajime INOUE, Ryuichi KANAMURA
  • Patent number: 10347673
    Abstract: The present disclosure relates to a solid-state imaging device and an electronic device that are configured to suppress the occurrence of noise and white blemishes in an amplification transistor having an element separation region which is formed by ion implantation. An amplification transistor has an element separation region formed by ion implantation. A channel region insulating film which is at least a part of a gate insulating film above a channel region of the amplification transistor is thin compared to a gate insulating film of a selection transistor, and an element separation region insulating film which is at least a part of a gate insulating film above the element separation region of the amplification transistor is thick compared to the channel region insulating film. The present disclosure can be applied to, for example, a CMOS image sensor, etc.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: July 9, 2019
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Yusuke Otake, Toshifumi Wakano, Takuya Sano, Yusuke Tanaka, Keiji Tatani, Hideo Harifuchi, Eiichi Tauchi, Hiroki Iwashita, Akira Matsumoto
  • Patent number: 10319758
    Abstract: A solid-state imaging device includes, in a semiconductor substrate, a pixel portion provided with a photoelectric conversion portion, which photoelectrically converts incident light to obtain an electric signal and a peripheral circuit portion disposed on the periphery of the pixel portion, wherein a gate insulating film of aMOS transistor in the peripheral circuit portion is composed of a silicon oxynitride film, a gate insulating film of aMOS transistor in the pixel portion is composed of a silicon oxynitride film, and an oxide film is disposed just above the photoelectric conversion portion in the pixel portion.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: June 11, 2019
    Assignee: Sony Corporation
    Inventors: Takuji Matsumoto, Keiji Tatani, Yasushi Tateshita, Kazuichiro Itonaga
  • Publication number: 20190109165
    Abstract: The present disclosure relates to a solid-state image sensor, an electronic apparatus and an imaging method by which specific processing other than normal processing can be sped up with reduced power consumption. The solid-state image sensor includes a pixel outputting a pixel signal used to construct an image and a logic circuit driving the pixel, and is configured of a stacked structure in which a first semiconductor substrate including a plurality of the pixels and a second semiconductor substrate including the logic circuit are joined together. In addition, among the plurality of pixels, a specific pixel is connected to the logic circuit independently of a normal pixel, the specific pixel being the pixel that outputs the pixel signal used in the specific processing other than imaging processing in which the image is imaged. The present technology can be applied to a stacked solid-state image sensor, for example.
    Type: Application
    Filed: December 7, 2018
    Publication date: April 11, 2019
    Applicant: SONY CORPORATION
    Inventors: Keiji TATANI, Tomoharu OGITA, Takashi NAGANO
  • Publication number: 20190057990
    Abstract: Solid-state imaging devices, methods of producing a solid-state imaging device, and electronic apparatuses are provided. More particularly, a solid-state image device includes a silicon substrate, and at least a first photodiode formed in the silicon substrate. The device also includes an epitaxial layer with a first surface adjacent a surface of the silicon substrate, and a transfer transistor with a gate electrode that extends from the at least a first photodiode to a second surface of the epitaxial layer opposite the first surface. In further embodiments, a solid-state imaging device with a plurality of pixels formed in a second semiconductor substrate wherein the pixels are symmetrical with respect to a center point is provided.
    Type: Application
    Filed: October 24, 2018
    Publication date: February 21, 2019
    Applicant: SONY CORPORATION
    Inventors: Yosuke TANAKA, Toshifumi WAKANO, Keiji TATANI, Takashi NAGANO, Hayato IWAMOTO, Keiichi NAKAZAWA, Tomoyuki HIRANO, Shinpei YAMAGUCHI, Shunsuke MARUYAMA
  • Publication number: 20190019824
    Abstract: Solid-state imaging devices, methods of producing a solid-state imaging device, and electronic apparatuses are provided. More particularly, a solid-state image device includes a silicon substrate, and at least a first photodiode formed in the silicon substrate. The device also includes an epitaxial layer with a first surface adjacent a surface of the silicon substrate, and a transfer transistor with a gate electrode that extends from the at least a first photodiode to a second surface of the epitaxial layer opposite the first surface. In further embodiments, a solid-state imaging device with a plurality of pixels formed in a second semiconductor substrate wherein the pixels are symmetrical with respect to a center point is provided.
    Type: Application
    Filed: September 4, 2018
    Publication date: January 17, 2019
    Applicant: SONY CORPORATION
    Inventors: Yosuke TANAKA, Toshifumi WAKANO, Keiji TATANI, Takashi NAGANO, Hayato IWAMOTO, Keiichi NAKAZAWA, Tomoyuki HIRANO, Shinpei YAMAGUCHI, Shunsuke MARUYAMA
  • Patent number: 10181485
    Abstract: The present disclosure relates to a solid-state image sensor, an electronic apparatus and an imaging method by which specific processing other than normal processing can be sped up with reduced power consumption. The solid-state image sensor includes a pixel outputting a pixel signal used to construct an image and a logic circuit driving the pixel, and is configured of a stacked structure in which a first semiconductor substrate including a plurality of the pixels and a second semiconductor substrate including the logic circuit are joined together. In addition, among the plurality of pixels, a specific pixel is connected to the logic circuit independently of a normal pixel, the specific pixel being the pixel that outputs the pixel signal used in the specific processing other than imaging processing in which the image is imaged. The present technology can be applied to a stacked solid-state image sensor, for example.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: January 15, 2019
    Assignee: Sony Corporation
    Inventors: Keiji Tatani, Tomoharu Ogita, Takashi Nagano
  • Publication number: 20180366502
    Abstract: A solid-state imaging device includes a first-conductivity-type semiconductor well region, a plurality of pixels each of which is formed on the semiconductor well region and is composed of a photoelectric conversion portion and a pixel transistor, an element isolation region provided between the pixels and in the pixels, and an element isolation region being free from an insulation film and being provided between desired pixel transistors.
    Type: Application
    Filed: August 28, 2018
    Publication date: December 20, 2018
    Applicant: Sony Corporation
    Inventors: Keiji Tatani, Fumihiko Koga, Takashi Nagano
  • Publication number: 20180350867
    Abstract: A semiconductor device including a first semiconductor section including a first wiring layer at one side thereof, the first semiconductor section further including a photodiode, a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together, a third semiconductor section including a third wiring layer at one side thereof, the second and the third semiconductor sections being secured together such the first semiconductor section, second semiconductor section, and the third semiconductor section are stacked together, and a first conductive material electrically connecting at least two of (i) the first wiring layer, (ii) the second wiring layer, and (iii) the third wiring layer such that the electrically connected wiring layers are in electrical communication.
    Type: Application
    Filed: July 23, 2018
    Publication date: December 6, 2018
    Applicant: SONY CORPORATION
    Inventors: Taku UMEBAYASHI, Keiji TATANI, Hajime INOUE, Ryuichi KANAMURA
  • Patent number: 10128301
    Abstract: A semiconductor device including a first semiconductor section including a first wiring layer at one side thereof, the first semiconductor section further including a photodiode, a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together, a third semiconductor section including a third wiring layer at one side thereof, the second and the third semiconductor sections being secured together such the first semiconductor section, second semiconductor section, and the third semiconductor section are stacked together, and a first conductive material electrically connecting at least two of (i) the first wiring layer, (ii) the second wiring layer, and (iii) the third wiring layer such that the electrically connected wiring layers are in electrical communication.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: November 13, 2018
    Assignee: Sony Corporation
    Inventors: Taku Umebayashi, Keiji Tatani, Hajime Inoue, Ryuichi Kanamura