Abstract: An isolator includes an insulation layer and a capacitor embedded in the insulation layer. The capacitor includes: a first electrode portion arranged in the insulation layer and connected to a first pad; a second electrode portion arranged in the insulation layer and connected to a second pad; and an intermediate electrode portion arranged in the insulation layer and not connected to the first electrode portion and the second electrode portion. The intermediate electrode portion includes a first intermediate layer, a second intermediate layer, and a connector connecting the first intermediate layer and the second intermediate layer. The capacitor is formed by coupling the first electrode portion and the second electrode portion through the intermediate electrode portion.

Abstract: An isolation transformer includes an insulation layer and a transformer. The transformer includes a first coil and a second coil embedded in the insulation layer. The first coil and the second coil are opposed to each other in a thickness-wise direction of the insulation layer. The first coil and the second coil include non-overlapping portions that do not overlap each other in the thickness-wise direction of the insulation layer.

Abstract: An insulating transformer comprising: an insulation layer; a transformer including a first coil embedded in the insulation layer and a second coil; and a capacitor including a first capacitor electrode and a second capacitor electrode, the first capacitor electrode being arranged between the first coil and the second coil and connected to a first ground terminal, and the second capacitor electrode being arranged between the first capacitor electrode and the second coil and connected to a second ground terminal.

Abstract: A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.

Abstract: A semiconductor device includes a semiconductor layer that has a principal surface, a first conductive layer that is formed on the principal surface of the semiconductor layer, a first insulating portion that is formed on the principal surface of the semiconductor layer so as to cover the first conductive layer and that includes a first insulating layer of at least three or more layers, a second insulating portion that is formed on the first insulating portion, that has a dielectric constant differing from a dielectric constant of the first insulating layer, and that includes a second insulating layer not included in the first insulating portion, and a second conductive layer that is formed on the second insulating portion, that faces the first conductive layer through the first insulating portion and the second insulating portion, and that is connected to a potential differing from a potential of the first conductive layer.

Abstract: A gate driver includes a low-voltage circuit configured to be actuated by application of a first voltage and a high-voltage circuit configured to be actuated by application of a second voltage that is higher than the first voltage. The gate driver also includes a transformer and a capacitor connected in series to the transformer. The low-voltage circuit and the high-voltage circuit are connected by the transformer and the capacitor and configured to transmit a signal through the transformer and the capacitor.

Abstract: A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.

Abstract: A semiconductor device includes a chip that has a first main surface on one side and a second main surface on another side, a pn-junction portion that is formed in an interior of the chip such as to extend along the first main surface, a device region that is provided in the first main surface, a first trench structure that is formed in the first main surface such as to penetrate through the pn-junction portion and demarcates the device region in the first main surface, and a second trench structure that is formed in the first main surface such as to penetrate through the pn-junction portion and demarcates the device region in a region further to the device region side than the first trench structure.

Abstract: A first main surface is a (000-1) plane or a plane inclined by an angle of less than or equal to 8° relative to the (000-1) plane. A reaction chamber has a cross-sectional area of more than or equal to 132 cm2 and less than or equal to 220 cm2 in a plane perpendicular to a direction of movement of a mixed gas. When an X axis indicates a first value and a Y axis indicates a second value, the first value and the second value fall within a hexagonal region surrounded by first coordinates, second coordinates, third coordinates, fourth coordinates, fifth coordinates and sixth coordinates in XY plane coordinates, where the first coordinates are (0.038, 0.0019), the second coordinates are (0.069, 0.0028), the third coordinates are (0.177, 0.0032), the fourth coordinates are (0.038, 0.0573), the fifth coordinates are (0.069, 0.0849), and the sixth coordinates are (0.177, 0.0964).

Abstract: A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.

Abstract: A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.

Abstract: A silicon carbide epitaxial substrate includes a silicon carbide single crystal substrate and a silicon carbide layer. In a direction parallel to a central region, a ratio of a standard deviation of a carrier concentration of the silicon carbide layer to an average value of the carrier concentration of the silicon carbide layer is less than 5%. The average value of the carrier concentration is more than or equal to 1×1014 cm?3 and less than or equal to 5×1016 cm?3. In the direction parallel to the central region, a ratio of a standard deviation of a thickness of the silicon carbide layer to an average value of the thickness of the silicon carbide layer is less than 5%. The central region has an arithmetic mean roughness (Sa) of less than or equal to 1 nm. The central region has a haze of less than or equal to 50.

Abstract: Provided is a gate driver that applies a gate voltage to a gate of a switching element, the gate driver including a low voltage circuit that operates when a first voltage is applied, a high voltage circuit that operates when a second voltage is applied, and an insulating chip, in which the insulating chip includes a substrate, an insulating layer, a first insulating element including a first conductor and a second conductor embedded into the insulating layer and arranged to face each other, and a second insulating element including a third conductor and a fourth conductor embedded into the insulating layer and arranged to face each other, and the low voltage circuit and the high voltage circuit are connected through the first insulating element and the second insulating element connected to each other in series and are configured to transmit signals through the first and second insulating elements.

Abstract: An electrostatic energy storage welding machine for performing resistance welding while applying pressure to an object to be welded includes: a pair of welding electrodes; an energy storage section including a plurality of energy storage parts; an individual charge circuit for individually charging respective energy storage parts; an individual discharge circuit for individually discharging the respective energy storage parts; a voltage monitor circuit individually monitoring voltages of the respective energy storage parts; an individual voltage stabilization control section for performing control to further charge an energy storage part having deviation in performance in an individual manner to stabilize a voltage of that energy storage part and thereby achieve a set voltage; and an output circuit for outputting power produced by the set voltage stabilized through individual charging and electric current through individual discharging in the energy storage section to apply the electric current between the we

Abstract: A sealing method that uses an electrostatic energy storage welding machine which includes an energy storage section including a plurality of energy storage parts is provided. A method of sealing a liquid inlet port of a power storage device includes burring in advance a through-hole of the liquid sealing port to raise a hole edge of the through-hole into a form of a projection, wherein the liquid sealing port of the power storage device to be sealed with electrolyte contained therein corresponds to an object to be welded; placing a spherical body that is a lid body on the projection; and performing resistance welding between the projection and the spherical body to seal the liquid inlet port.

Abstract: A first main surface is a (000-1) plane or a plane inclined by an angle of less than or equal to 8° relative to the (000-1) plane. A reaction chamber has a cross-sectional area of more than or equal to 132 cm2 and less than or equal to 220 cm2 in a plane perpendicular to a direction of movement of a mixed gas. When an X axis indicates a first value and a Y axis indicates a second value, the first value and the second value fall within a hexagonal region surrounded by first coordinates, second coordinates, third coordinates, fourth coordinates, fifth coordinates and sixth coordinates in XY plane coordinates, where the first coordinates are (0.038, 0.0019), the second coordinates are (0.069, 0.0028), the third coordinates are (0.177, 0.0032), the fourth coordinates are (0.038, 0.0573), the fifth coordinates are (0.069, 0.0849), and the sixth coordinates are (0.177, 0.0964).

Abstract: The operation information acquisition device includes the external detection device which is provided on the outer side of the main body frame of the sewing machine and detects the state change of the operating member that performs the periodic operation at the same cycle as the up-down movement operation of the sewing needle, the operation information acquisition device acquires operation information based on detection result of the external detection device. The operation information acquisition device can acquire the operation information such as the “number of stitches”, the “operating hours”, the “sewing speed”, and the “number of times of thread cutting”.

Abstract: A silicon carbide epitaxial substrate includes a silicon carbide single crystal substrate and a silicon carbide layer. In a direction parallel to a central region, a ratio of a standard deviation of a carrier concentration of the silicon carbide layer to an average value of the carrier concentration of the silicon carbide layer is less than 5%. The average value of the carrier concentration is more than or equal to 1×1014 cm?3 and less than or equal to 5×1016 cm?3. In the direction parallel to the central region, a ratio of a standard deviation of a thickness of the silicon carbide layer to an average value of the thickness of the silicon carbide layer is less than 5%. The central region has an arithmetic mean roughness (Sa) of less than or equal to 1 nm. The central region has a haze of less than or equal to 50.

Abstract: A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.

Abstract: A silicon carbide epitaxial substrate includes a silicon carbide single crystal substrate and a silicon carbide layer. In a direction parallel to a central region, a ratio of a standard deviation of a carrier concentration of the silicon carbide layer to an average value of the carrier concentration of the silicon carbide layer is less than 5%. The average value of the carrier concentration is more than or equal to 1×1014 cm?3 and less than or equal to 5×1016 cm?3. In the direction parallel to the central region, a ratio of a standard deviation of a thickness of the silicon carbide layer to an average value of the thickness of the silicon carbide layer is less than 5%. The central region has an arithmetic mean roughness (Sa) of less than or equal to 1 nm. The central region has a haze of less than or equal to 50.