Abstract: A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.

Abstract: A semiconductor device includes: a first chip including a first circuit; a second chip disposed to be spaced apart from the first chip in a first direction and including a second circuit; and a transformer chip disposed over the first chip and including a transformer. The first circuit and the second circuit are configured to transmit a signal or power via the transformer. The transformer chip includes: an element insulating layer; and an outer coil and an inner coil disposed as the transformer in the element insulating layer. The inner coil is disposed inside the outer coil so as not to overlap the outer coil when viewed from a thickness direction of the element insulating layer.

Abstract: A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.

Abstract: The operation information acquisition device includes the external detection device which is provided on the outer side of the main body frame of the sewing machine and detects the state change of the operating member that performs the periodic operation at the same cycle as the up-down movement operation of the sewing needle, the operation information acquisition device acquires operation information based on detection result of the external detection device. The operation information acquisition device can acquire the operation information such as the “number of stitches”, the “operating hours”, the “sewing speed”, and the “number of times of thread cutting”.

Abstract: A semiconductor device includes a substrate, a lower insulating film that is formed on the substrate, a resistor that is formed on the lower insulating film, and an upper insulating film that is formed on the lower insulating film such as to cover the resistor. The lower insulating film includes a first nitride film and a first SiO-based insulating film that is formed on the first nitride film and the upper insulating film includes a second nitride film. The resistor is formed on the first SiO-based insulating film and a lower surface of a peripheral edge portion of the second nitride film is joined to an upper surface of the first nitride film.

Abstract: An insulation chip includes a first unit, second unit provided on the first unit, and an insulating bonding material for bonding the first and second units. The first unit includes a first element insulating layer including a first element front surface facing the second unit and a first element back surface, and a first insulating element buried in the first element insulating layer at a position spaced apart from the first element front surface in a thickness direction of the first element insulating layer. The second unit includes a second element insulating layer including a second element front surface and a second element back surface, a second insulating element buried in the second element insulating layer at a position spaced apart from the second element front surface in a thickness direction of the second element insulating layer, and a second semiconductor substrate in contact with the second element back surface.

Abstract: An insulation chip includes first and second units bonded to each other. The first unit includes a first semiconductor substrate, a first element insulating layer including a first element front surface facing the second unit and a first element back surface, and first and fourth insulating elements buried in the first element insulating layer at positions spaced apart from the first element front surface. The second unit includes a second element insulating layer having a second element front surface and a second element back surface, and second and third insulating elements buried in the second element insulating layer at positions spaced apart from the second element front surface. When the second unit is bonded to the first unit, the first and second insulating elements are arranged to face each other, and the third and fourth insulating elements are arranged to face each other.

Abstract: An insulation chip includes a first unit, and a second unit bonded to the first unit and smaller in size than the first unit in a plan view. The first unit includes a first element insulating layer, a first insulating element buried in the first element insulating layer, and a first electrode pad provided on the first element insulating layer. The second unit includes a second element insulating layer, and a second insulating element buried in the second element insulating layer. In a unit bonding state in which the second unit is bonded to the first unit, the first and second insulating elements are arranged to face each other in a thickness direction of the first element insulating layer, and the first electrode pad is provided at a different position from the second unit in a plan view.

Abstract: A semiconductor device includes a die pad, a first semiconductor element and a second semiconductor element each mounted on the die pad, and an insulating element electrically connected to the first semiconductor element and the second semiconductor element and insulating the first semiconductor element and the second semiconductor element from each other. The semiconductor device further includes a dummy element bonded to the die pad and a first bonding layer bonding the dummy element and the insulating element. The dummy element includes an insulating layer located between the die pad and the first bonding layer in a thickness direction.

Abstract: A first resistor circuit includes a plurality of first resistors that extend in a first direction and are disposed at intervals in a second direction orthogonal to the first direction in plan view, a second resistor circuit includes one second resistor that extends in the first direction or a plurality of second resistors that extend in the first direction and are disposed at intervals in the second direction, a third resistor circuit includes one third resistor that extends in the first direction or a plurality of third resistors that extend in the first direction and are disposed at intervals in the second direction, a fourth resistor circuit includes a plurality of fourth resistors that extend in the first direction and are disposed at intervals in the second direction, the second resistors include one or a plurality of intermediate second resistors disposed between two first resistors adjacent in the second direction among the plurality of first resistors, and the third resistors include one or a pluralit

Abstract: A sealing method that uses an electrostatic energy storage welding machine which includes an energy storage section including a plurality of energy storage parts is provided. A method of sealing a liquid inlet port of a power storage device includes burring in advance a through-hole of the liquid sealing port to raise a hole edge of the through-hole into a form of a projection, wherein the liquid sealing port of the power storage device to be sealed with electrolyte contained therein corresponds to an object to be welded; placing a spherical body that is a lid body on the projection; and performing resistance welding between the projection and the spherical body to seal the liquid inlet port.

Abstract: A first main surface is a (000-1) plane or a plane inclined by an angle of less than or equal to 8° relative to the (000-1) plane. A substrate placement surface has an area of more than or equal to 697 cm2 and less than or equal to 1161 cm2. When an X axis indicates a first value and a Y axis indicates a second value, the first value and the second value fall within a hexagonal region surrounded by first coordinates, second coordinates, third coordinates, fourth coordinates, fifth coordinates and sixth coordinates in XY plane coordinates, where the first coordinates are (0.038, 0.0019), the second coordinates are (0.069, 0.0028), the third coordinates are (0.177, 0.0032), the fourth coordinates are (0.038, 0.0573), the fifth coordinates are (0.069, 0.0849), and the sixth coordinates are (0.177, 0.0964).

Abstract: An electronic component includes an underlay resin, and a pad electrode that has a sidewall located on the underlay resin and an uneven portion formed at a lower end portion of the sidewall.

Abstract: A transformer chip of a signal transmitting device has a substrate, an element insulation layer, and a first transformer and a second transformer provided within the element insulation layer. The first transformer comprises a first coil, and a second coil positioned facing the first coil in the z direction. The second transformer comprises a first coil, and a second coil positioned facing the first coil in the z direction. The second coil of the first transformer and the second coil of the second transformer are electrically connected. The transformer chip comprises a back surface insulating layer provided on the back surface of the substrate.

Abstract: An isolator includes an insulation layer and a capacitor embedded in the insulation layer. The capacitor includes: a first electrode portion arranged in the insulation layer and connected to a first pad; a second electrode portion arranged in the insulation layer and connected to a second pad; and an intermediate electrode portion arranged in the insulation layer and not connected to the first electrode portion and the second electrode portion. The intermediate electrode portion includes a first intermediate layer, a second intermediate layer, and a connector connecting the first intermediate layer and the second intermediate layer. The capacitor is formed by coupling the first electrode portion and the second electrode portion through the intermediate electrode portion.

Abstract: An isolation transformer includes an insulation layer and a transformer. The transformer includes a first coil and a second coil embedded in the insulation layer. The first coil and the second coil are opposed to each other in a thickness-wise direction of the insulation layer. The first coil and the second coil include non-overlapping portions that do not overlap each other in the thickness-wise direction of the insulation layer.

Abstract: A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.

Abstract: An insulating transformer comprising: an insulation layer; a transformer including a first coil embedded in the insulation layer and a second coil; and a capacitor including a first capacitor electrode and a second capacitor electrode, the first capacitor electrode being arranged between the first coil and the second coil and connected to a first ground terminal, and the second capacitor electrode being arranged between the first capacitor electrode and the second coil and connected to a second ground terminal.

Abstract: A semiconductor device includes a semiconductor layer that has a principal surface, a first conductive layer that is formed on the principal surface of the semiconductor layer, a first insulating portion that is formed on the principal surface of the semiconductor layer so as to cover the first conductive layer and that includes a first insulating layer of at least three or more layers, a second insulating portion that is formed on the first insulating portion, that has a dielectric constant differing from a dielectric constant of the first insulating layer, and that includes a second insulating layer not included in the first insulating portion, and a second conductive layer that is formed on the second insulating portion, that faces the first conductive layer through the first insulating portion and the second insulating portion, and that is connected to a potential differing from a potential of the first conductive layer.

Abstract: A gate driver includes a low-voltage circuit configured to be actuated by application of a first voltage and a high-voltage circuit configured to be actuated by application of a second voltage that is higher than the first voltage. The gate driver also includes a transformer and a capacitor connected in series to the transformer. The low-voltage circuit and the high-voltage circuit are connected by the transformer and the capacitor and configured to transmit a signal through the transformer and the capacitor.