Patents by Inventor Keiko Ariyoshi
Keiko Ariyoshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10249717Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, first to fourth semiconductor regions and a first insulating film. The second electrode includes first, second, and third electrode regions. The first semiconductor region includes first, second, third, fourth, and fifth partial regions. The first partial region is separated from the first electrode. The second partial region is separated from the first electrode region. The fourth partial region is separated from the second electrode region. The second semiconductor region includes sixth, seventh, eighth and ninth partial regions. The third semiconductor region is connected to the second semiconductor region. The fourth semiconductor region is electrically connected to the second electrode. The fourth semiconductor region includes tenth, eleventh, and twelfth partial regions. The first insulating film is provided between the first, third, and fourth semiconductor regions.Type: GrantFiled: January 30, 2018Date of Patent: April 2, 2019Assignees: Kabushiki Kaisha Toshiba, Fuji Electric Co., Ltd.Inventors: Keiko Ariyoshi, Ryosuke Iijima, Shinya Kyogoku, Shinsuke Harada, Yusuke Kobayashi
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Patent number: 10236339Abstract: According to one embodiment, a semiconductor device includes first to sixth semiconductor regions, a first electrode, and a first insulating film. The first semiconductor region includes first and second partial regions. The second semiconductor region is separated from the first partial region in a second direction crossing a first direction. The third semiconductor region is provided between the first partial region and the second semiconductor region. The fourth semiconductor region is provided between the first partial region and the third semiconductor region. The first electrode is separated from the second partial region, the second and third semiconductor regions, and a portion of the fourth semiconductor region. The first insulating film contacts the third semiconductor region. The fifth semiconductor region is provided between the first insulating film and the second partial region. The sixth semiconductor region is provided between the first insulating film and the fifth semiconductor region.Type: GrantFiled: August 31, 2017Date of Patent: March 19, 2019Assignee: Kabushiki Kaisha ToshibaInventors: Shinya Kyogoku, Ryosuke Iijima, Keiko Ariyoshi
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Publication number: 20180219070Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, first to fourth semiconductor regions and a first insulating film. The second electrode includes first, second, and third electrode regions. The first semiconductor region includes first, second, third, fourth, and fifth partial regions. The first partial region is separated from the first electrode. The second partial region is separated from the first electrode region. The fourth partial region is separated from the second electrode region. The second semiconductor region includes sixth, seventh, eighth and ninth partial regions. The third semiconductor region is connected to the second semiconductor region. The fourth semiconductor region is electrically connected to the second electrode. The fourth semiconductor region includes tenth, eleventh, and twelfth partial regions. The first insulating film is provided between the first, third, and fourth semiconductor regions.Type: ApplicationFiled: January 30, 2018Publication date: August 2, 2018Applicants: Kabushiki Kaisha Toshiba, Fuji Electric Co., Ltd.Inventors: Keiko ARIYOSHI, Ryosuke IIJIMA, Sinya KYOGOKU, Shinsuke HARADA, Yusuke KOBAYASHI
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Patent number: 9978842Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a first electrode, a second electrode, a control electrode and an insulating film. The first semiconductor region is of a first conductivity type and includes SiC. The second semiconductor region is provided on the first semiconductor region and has a first surface. The second semiconductor region is of a second conductivity type and includes SiC. The third semiconductor region is provided on the second semiconductor region, is of the first conductivity type and includes SiC. The first and second electrodes are electrically connected to the third semiconductor region. The control electrode is provided on the second semiconductor region. The insulating film is provided between the second semiconductor region and the control electrode. The insulating film contacts the first surface and the control electrode and includes nitrogen.Type: GrantFiled: March 16, 2016Date of Patent: May 22, 2018Assignees: Kabushiki Kaisha Toshiba, National Institute of Advanced Industrial Science and Technology, FUJI ELECTRIC CO., LTD.Inventors: Keiko Ariyoshi, Tatsuo Shimizu, Takashi Shinohe, Junji Senzaki, Shinsuke Harada, Takahito Kojima
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Publication number: 20180083094Abstract: According to one embodiment, a semiconductor device includes first to sixth semiconductor regions, a first electrode, and a first insulating film. The first semiconductor region includes first and second partial regions. The second semiconductor region is separated from the first partial region in a second direction crossing a first direction. The third semiconductor region is provided between the first partial region and the second semiconductor region. The fourth semiconductor region is provided between the first partial region and the third semiconductor region. The first electrode is separated from the second partial region, the second and third semiconductor regions, and a portion of the fourth semiconductor region. The first insulating film contacts the third semiconductor region. The fifth semiconductor region is provided between the first insulating film and the second partial region. The sixth semiconductor region is provided between the first insulating film and the fifth semiconductor region.Type: ApplicationFiled: August 31, 2017Publication date: March 22, 2018Applicant: Kabushiki Kaisha ToshibaInventors: Shinya Kyogoku, Ryosuke lijima, Keiko Ariyoshi
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Patent number: 9825121Abstract: A semiconductor device of the embodiment includes an SiC layer of 4H—SiC structure having a surface inclined at an angle from 0 degree to 30 degrees relative to {11-20} face or {1-100} face, a gate electrode, a gate insulating film provided between the surface and the gate electrode, a n-type first SiC region provided in the SiC layer, a n-type second SiC region provided in the SiC layer, a channel forming region provided in the SiC layer between the first SiC region and the second SiC region, the channel forming region provided adjacent to the surface, and the channel forming region having a direction inclined at an angle from 60 degrees to 90 degrees relative to a <0001> direction or a <000-1> direction.Type: GrantFiled: December 16, 2015Date of Patent: November 21, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Ryosuke Iijima, Keiko Ariyoshi, Tatsuo Shimizu, Kazuto Takao, Takashi Shinohe
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Publication number: 20160197150Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a first electrode, a second electrode, a control electrode and an insulating film. The first semiconductor region is of a first conductivity type and includes SiC. The second semiconductor region is provided on the first semiconductor region and has a first surface. The second semiconductor region is of a second conductivity type and includes SiC. The third semiconductor region is provided on the second semiconductor region, is of the first conductivity type and includes SiC. The first and second electrodes are electrically connected to the third semiconductor region. The control electrode is provided on the second semiconductor region. The insulating film is provided between the second semiconductor region and the control electrode. The insulating film contacts the first surface and the control electrode and includes nitrogen.Type: ApplicationFiled: March 16, 2016Publication date: July 7, 2016Inventors: Keiko ARIYOSHI, Tatsuo SHIMIZU, Takashi SHINOHE, Junji SENZAKI, Shinsuke HARADA, Takahito KOJIMA
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Publication number: 20160190234Abstract: A semiconductor device of the embodiment includes an SiC layer of 4H-SiC structure having a surface inclined at an angle from 0 degree to 30 degrees relative to {11-20} face or {1-100} face, a gate electrode, a gate insulating film provided between the surface and the gate electrode, a n-type first SiC region provided in the SiC layer, a n-type second SiC region provided in the SiC layer, a channel forming region provided in the SiC layer between the first SiC region and the second SiC region, the channel forming region provided adjacent to the surface, and the channel forming region having a direction inclined at an angle from 60 degrees to 90 degrees relative to a <0001> direction or a <000-1> direction.Type: ApplicationFiled: December 16, 2015Publication date: June 30, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Ryosuke IIJIMA, Keiko Ariyoshi, Tatsuo Shimizu, Kazuto Takao, Takashi Shinohe
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Patent number: 9269781Abstract: According to one embodiment, a semiconductor device includes a first, a second, a third, a fourth semiconductor region, a control electrode, and an insulating film. The first region contains silicon carbide. The second region is provided on the first region and contains silicon carbide. The third region is provided on the second region and contains silicon carbide. The fourth region is provided on the third region and contains silicon carbide. The control electrode is provided in a trench. The trench is formed in the fourth, the third, and the second semiconductor region. The insulating film is provided between a side surface of the trench and the control electrode. The insulating film contains a high-dielectric constant region. The high-dielectric constant region contacts with at least the third semiconductor region. The high-dielectric constant region has a higher dielectric constant than a dielectric constant of silicon oxide.Type: GrantFiled: December 2, 2014Date of Patent: February 23, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Keiko Ariyoshi, Takuma Suzuki, Takashi Shinohe
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Publication number: 20150087124Abstract: According to one embodiment, a semiconductor device includes a first, a second, a third, a fourth semiconductor region, a control electrode, and an insulating film. The first region contains silicon carbide. The second region is provided on the first region and contains silicon carbide. The third region is provided on the second region and contains silicon carbide. The fourth region is provided on the third region and contains silicon carbide. The control electrode is provided in a trench. The trench is formed in the fourth, the third, and the second semiconductor region. The insulating film is provided between a side surface of the trench and the control electrode. The insulating film contains a high-dielectric constant region. The high-dielectric constant region contacts with at least the third semiconductor region. The high-dielectric constant region has a higher dielectric constant than a dielectric constant of silicon oxide.Type: ApplicationFiled: December 2, 2014Publication date: March 26, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Keiko ARIYOSHI, Takuma SUZUKI, Takashi SHINOHE
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Patent number: 8941120Abstract: According to one embodiment, a semiconductor device includes a first, a second, a third, a fourth semiconductor region, a control electrode, and an insulating film. The first region contains silicon carbide. The second region is provided on the first region and contains silicon carbide. The third region is provided on the second region and contains silicon carbide. The fourth region is provided on the third region and contains silicon carbide. The control electrode is provided in a trench. The trench is formed in the fourth, the third, and the second semiconductor region. The insulating film is provided between a side surface of the trench and the control electrode. The insulating film contains a high-dielectric constant region. The high-dielectric constant region contacts with at least the third semiconductor region. The high-dielectric constant region has a higher dielectric constant than a dielectric constant of silicon oxide.Type: GrantFiled: December 14, 2012Date of Patent: January 27, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Keiko Ariyoshi, Takuma Suzuki, Takashi Shinohe
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Publication number: 20130248880Abstract: According to one embodiment, a semiconductor device includes a first, a second, a third, and a fourth semiconductor region, a control electrode, a floating electrode, and an insulating film. The first region contains silicon carbide. The second region is provided on the first region and contains silicon carbide. The third region is provided on the second region and contains silicon carbide. The fourth region is provided on the third region and contains silicon carbide. The control electrode is provided in a trench formed in the fourth, the third, and the second region. The floating electrode is provided between the control electrode and a bottom surface of the trench. The insulating film is provided between the trench and the control electrode, between the trench and the floating electrode, and between the control electrode and the floating electrode.Type: ApplicationFiled: August 31, 2012Publication date: September 26, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Keiko ARIYOSHI, Takuma Suzuki, Hiroshi Kono, Takashi Shinohe
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Publication number: 20130248881Abstract: According to one embodiment, a semiconductor device includes a first, a second, a third, a fourth semiconductor region, a control electrode, and an insulating film. The first region contains silicon carbide. The second region is provided on the first region and contains silicon carbide. The third region is provided on the second region and contains silicon carbide. The fourth region is provided on the third region and contains silicon carbide. The control electrode is provided in a trench. The trench is formed in the fourth, the third, and the second semiconductor region. The insulating film is provided between a side surface of the trench and the control electrode. The insulating film contains a high-dielectric constant region. The high-dielectric constant region contacts with at least the third semiconductor region. The high-dielectric constant region has a higher dielectric constant than a dielectric constant of silicon oxide.Type: ApplicationFiled: December 14, 2012Publication date: September 26, 2013Inventors: Keiko ARIYOSHI, Takuma Suzuki, Takashi Shinohe
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Patent number: 7943981Abstract: A semiconductor memory element includes: a tunnel insulating film formed on a semiconductor substrate; a HfON charge storage film with Bevan clusters formed on the tunnel insulating film; a blocking film formed on the HfON charge storage film; and a gate electrode formed on the blocking film.Type: GrantFiled: September 18, 2008Date of Patent: May 17, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Tsunehiro Ino, Naoki Yasuda, Koichi Muraoka, Jun Fujiki, Shoko Kikuchi, Keiko Ariyoshi
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Patent number: 7804128Abstract: A nonvolatile semiconductor memory device according to an example of the present invention includes a semiconductor region, source/drain areas arranged separately in the semiconductor region, a tunnel insulating film arranged on a channel region between the source/drain areas, a floating gate electrode arranged on the tunnel insulating film, an inter-electrode insulating film arranged on the floating gate electrode, and a control gate electrode arranged on the inter-electrode insulating film. The inter-electrode insulating film includes La, Al and Si.Type: GrantFiled: August 27, 2008Date of Patent: September 28, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Keiko Ariyoshi, Akira Takashima, Shoko Kikuchi, Koichi Muraoka
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Publication number: 20100032747Abstract: A semiconductor memory device includes a plurality of memory cell transistors each having a gate electrode section including a charge accumulation layer formed on a semiconductor substrate via a gate insulating film, a first insulating film formed using a material with a higher dielectric constant than the gate insulating film, a control gate, an impurity diffusion layer functioning as a source or a drain, and a plurality of barrier films formed on a side surface of the gate electrode section so as to cover a side surface of at least the first insulating film and formed between the first insulating film and the control gate. The device further includes a plurality of second insulating films formed on the semiconductor substrate and each formed between the gate electrode sections of adjacent ones of the plurality of memory cell transistors.Type: ApplicationFiled: July 21, 2009Publication date: February 11, 2010Inventors: Takayuki OKAMURA, Keiko Ariyoshi
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Publication number: 20090212346Abstract: A semiconductor memory element includes: a tunnel insulating film formed on a semiconductor substrate; a HfON charge storage film with Bevan clusters formed on the tunnel insulating film; a blocking film formed on the HfON charge storage film; and a gate electrode formed on the blocking film.Type: ApplicationFiled: September 18, 2008Publication date: August 27, 2009Applicant: Kabushiki Kaisha ToshibaInventors: Tsunehiro INO, Naoki Yasuda, Koichi Muraoka, Jun Fujiki, Shoko Kikuchi, Keiko Ariyoshi
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Publication number: 20090206393Abstract: A nonvolatile memory element includes a semiconductor region, a source region and a drain region provided in the semiconductor region, a tunnel insulating layer provided on the semiconductor region between the source region and the drain region, a charge storage layer provided on the tunnel insulating layer, a block insulating layer provided on the charge storage layer, and a control gate electrode provided on the block insulating layer. The charge storage layer includes one of an oxide, a nitride and an oxynitride, which contains at least one material selected from the group consisting of Hf, Al, Zr, Ti and a rare-earth metal, and is entirely or partially crystallized. The block insulating layer includes one of an oxide, an oxynitride, a silicate and an aluminate, which contains at least one rare-earth metal.Type: ApplicationFiled: February 18, 2009Publication date: August 20, 2009Inventors: Keiko Ariyoshi, Akira Takashima, Shoko Kikuchi, Koichi Muraoka
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Publication number: 20090057751Abstract: A nonvolatile semiconductor memory device according to an example of the present invention includes a semiconductor region, source/drain areas arranged separately in the semiconductor region, a tunnel insulating film arranged on a channel region between the source/drain areas, a floating gate electrode arranged on the tunnel insulating film, an inter-electrode insulating film arranged on the floating gate electrode, and a control gate electrode arranged on the inter-electrode insulating film. The inter-electrode insulating film includes La, Al and Si.Type: ApplicationFiled: August 27, 2008Publication date: March 5, 2009Inventors: Keiko ARIYOSHI, Akira TAKASHIMA, Shoko KIKUCHI, Koichi MURAOKA