Patents by Inventor Keiko Fujihira

Keiko Fujihira has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8222649
    Abstract: A semiconductor device and a method of manufacturing the same, to appropriately determine an impurity concentration distribution of a field relieving region and reduce an ON-resistance. The semiconductor device includes a substrate, a first drift layer, a second drift layer, a first well region, a second well region, a current control region, and a field relieving region. The first well region is disposed continuously from an end portion adjacent to the vicinity of outer peripheral portion of the second drift layer to a portion of the first drift layer below the vicinity of outer peripheral portion. The field relieving region is so disposed in the first drift layer as to be adjacent to the first well region.
    Type: Grant
    Filed: November 17, 2006
    Date of Patent: July 17, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventors: Naruhisa Miura, Keiko Fujihira, Kenichi Otsuka, Masayuki Imaizumi
  • Patent number: 7928469
    Abstract: The present invention provides a MOSFET and so forth that offer high breakdown voltage and low on-state loss (high channel mobility and low gate threshold voltage) and that can easily achieve normally OFF. A drift layer 2 of a MOSFET made of silicon carbide according to the present invention has a first region 2a and a second region 2b. The first region 2a is a region from the surface to a first given depth. The second region 2b is formed in a region deeper than the first given depth. The impurity concentration of the first region 2a is lower than the impurity concentration of the second region 2b.
    Type: Grant
    Filed: October 6, 2006
    Date of Patent: April 19, 2011
    Assignee: Mitsubishi Electric Corporation
    Inventors: Keiko Fujihira, Naruhisa Miura, Kenichi Ohtsuka, Masayuki Imaizumi
  • Publication number: 20100219417
    Abstract: A semiconductor device and a method of manufacturing the same, to appropriately determine an impurity concentration distribution of a field relieving region and reduce an ON-resistance. The semiconductor device includes a substrate, a first drift layer, a second drift layer, a first well region, a second well region, a current control region, and a field relieving region. The first well region is disposed continuously from an end portion adjacent to the vicinity of outer peripheral portion of the second drift layer to a portion of the first drift layer below the vicinity of outer peripheral portion. The field relieving region is so disposed in the first drift layer as to be adjacent to the first well region.
    Type: Application
    Filed: November 17, 2006
    Publication date: September 2, 2010
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Naruhisa Miura, Keiko Fujihira, Kenichi Otsuka, Masayuki Imaizumi
  • Publication number: 20090173997
    Abstract: The present invention provides a MOSFET and so forth that offer high breakdown voltage and low on-state loss (high channel mobility and low gate threshold voltage) and that can easily achieve normally OFF. A drift layer 2 of a MOSFET made of silicon carbide according to the present invention has a first region 2a and a second region 2b. The first region 2a is a region from the surface to a first given depth. The second region 2b is formed in a region deeper than the first given depth. The impurity concentration of the first region 2a is lower than the impurity concentration of the second region 2b.
    Type: Application
    Filed: October 6, 2006
    Publication date: July 9, 2009
    Applicant: Mitsubishi Electric Corporation
    Inventors: Keiko Fujihira, Naruhisa Miura, Kenichi Ohtsuka, Masayuki Imaizumi