Abstract: Provided are: a prepolymer which is capable of forming a non-linear optical material that has excellent non-linear optical effect, heat resistance, withstand voltage and transparency; a curable material which contains the prepolymer; a coating composition which contains the curable material and a solvent; a non-linear optical material which is obtained by curing the curable material; an optical waveguide which uses the non-linear optical material; and a light control device which is provided with the optical waveguide. The present invention uses a prepolymer having a crosslinkable functional group, which is obtained by reacting one or more compounds (X) that are selected from the group consisting of compounds (X1), compounds (X2) and compounds (X3), a compound (Y) that is represented by formula (Y), a compound (Z) that has three or more phenolic hydroxyl groups, and an organic compound (B) that exerts a non-linear optical effect and has a reactive group.

Abstract: Provided are: a prepolymer which is capable of forming a non-linear optical material that has excellent non-linear optical effect, heat resistance, withstand voltage and transparency; a curable material which contains the prepolymer; a coating composition which contains the curable material and a solvent; a non-linear optical material which is obtained by curing the curable material; an optical waveguide which uses the non-linear optical material; and a light control device which is provided with the optical waveguide. The present invention uses a prepolymer having a crosslinkable functional group, which is obtained by reacting one or more compounds (X) that are selected from the group consisting of compounds (X1), compounds (X2) and compounds (X3), a compound (Y) that is represented by formula (Y), a compound (Z) that has three or more phenolic hydroxyl groups, and an organic compound (B) that exerts a non-linear optical effect and has a reactive group.

Abstract: A semiconductor integrated circuit device includes a first clock domain having a plurality of first flip-flops which is configured to operate with a high-speed clock; a second clock domain having a plurality of second flip-flops, composed of a third flip-flop and a plurality of fourth flip-flops, which is configured to operate with a low-speed clock; and a test clock supplying section configured to supply, at a time of delay fault test for the second clock domain, a test clock based on the high-speed clock to the third flip-flop to which data from the first clock domain is input, and not to supply the test clock to the plurality of fourth flip-flops.

Abstract: A semiconductor integrated circuit includes: a first boundary cell having a first power source wiring, a second power source wiring and a first pseudo power source wiring; a first circuit cell having a third power source wiring connected with the first power source wiring, a second pseudo power source wiring connected with the first pseudo power source wiring, and a first circuit formed of a first circuit transistor; and a first switching transistor having a first electrode connected with the second power source wiring, a second electrode connected with the first pseudo power source wiring, and a gate electrode, wherein the first switching transistor is operated to be turned “ON” and “OFF” according to a control signal inputted to the gate electrode of the first switching transistor and an absolute value of a threshold voltage of the first switching transistor is larger than an absolute value of a threshold voltage of the first circuit transistor.

Abstract: A semiconductor integrated circuit device includes a first clock domain having a plurality of first flip-flops which is configured to operate with a high-speed clock; a second clock domain having a plurality of second flip-flops, composed of a third flip-flop and a plurality of fourth flip-flops, which is configured to operate with a low-speed clock; and a test clock supplying section configured to supply, at a time of delay fault test for the second clock domain, a test clock based on the high-speed clock to the third flip-flop to which data from the first clock domain is input, and not to supply the test clock to the plurality of fourth flip-flops.

Abstract: A semiconductor integrated circuit includes: a first boundary cell having a first power source wiring, a second power source wiring and a first pseudo power source wiring; a first circuit cell having a third power source wiring connected with the first power source wiring, a second pseudo power source wiring connected with the first pseudo power source wiring, and a first circuit formed of a first circuit transistor; and a first switching transistor having a first electrode connected with the second power source wiring, a second electrode connected with the first pseudo power source wiring, and a gate electrode, wherein the first switching transistor is operated to be turned “ON” and “OFF” according to a control signal inputted to the gate electrode of the first switching transistor and an absolute value of a threshold voltage of the first switching transistor is larger than an absolute value of a threshold voltage of the first circuit transistor.

Abstract: A constant current is formed by supplying voltage differences between bases and emitters of a first transistor which allows a first current to flow in the emitter thereof and a second transistor which allows a second current having a current density larger than a current density of the first transistor to flow in an emitter thereof to a first resistance. A second resistance is provided on a ground potential side of a circuit in series with the first resistance. A third and a fourth resistances are provided between collectors and the power supply voltages of the first transistor and the second transistor. Both collector voltages of the first and second transistors are supplied to a differential amplifier circuit having the CMOS constitution thus forming an output voltage and, at the same time, the output voltage is supplied to bases of the first transistor and the second transistor in common.

Abstract: A semiconductor integrated circuit device has a plurality of functional blocks. Each of the plurality of functional blocks comprises a DLL circuit for outputting a clock signal, at least one wiring portion for receiving the clock signal at one end thereof, and at least one load circuit for receiving the clock signal from the DLL circuit via the wiring portion. The DLL circuit receives a reference clock signal and a wiring portion and outputs the clock signal so that the phase difference between the reference clock signal and the second clock signal is a predetermined value. Thus, clock skew is reduced even if there is variation due to process.