Patents by Inventor Keiko Ikuta

Keiko Ikuta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230089483
    Abstract: A method for manufacturing a semiconductor device includes providing a semiconductor element having an electrode terminal, forming a resist on the semiconductor element, the resist having a first surface facing the electrode terminal and a second surface opposite to the first surface, providing an imprint mold having a third surface and a protrusion protruding from the third surface, forming an opening in the resist by disposing the imprint mold on the second surface of the resist and inserting the protrusion into the resist, the third surface of the imprint mold facing the second surface of the resist, the protrusion being aligned with the electrode terminal, curing the resist by applying energy to the resist, widening the opening in a radial direction of the opening by causing the resist to react with a developer, and forming a bump by filling the opening with metal, in which the forming of the opening in the resist is performed in a state where a gap is provided between the second surface of the resist and
    Type: Application
    Filed: August 23, 2022
    Publication date: March 23, 2023
    Inventors: KIYOKAZU ITOI, KEIKO IKUTA, DAISUKE SAKURAI
  • Patent number: 9076752
    Abstract: A semiconductor device (1) includes: a semiconductor chip (2) having a first main surface and a second main surface opposite to the first main surface; a heat dissipating plate (3) opposed to the first main surface; a first electrode (5) disposed between the first main surface and the heat dissipating plate (3) so as to be electrically connected to the semiconductor chip (2); a pressure contact member (4) opposed to the second main surface; a second electrode (6) disposed between the second main surface and the pressure contact member (4) so as to be electrically connected to the semiconductor chip (2); and a pressure generating mechanism that generates a pressure for pressing the first electrode (5) into contact with the heat dissipating plate (3) and the semiconductor chip (2) and pressing the second electrode (6) into contact with the pressure contact member (4) and the semiconductor chip (2).
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: July 7, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Toshiyuki Kojima, Tsukasa Shiraishi, Norihito Tsukahara, Takayuki Hirose, Keiko Ikuta, Masayoshi Koyama
  • Patent number: 9018035
    Abstract: A pressed-contact type semiconductor device includes a power semiconductor element, on an upper surface of which at least a first electrode is formed and on a lower surface of which at least a second electrode is formed, lead frames which face the first electrode and the second electrode of the power semiconductor element respectively, and a clip which applies a pressure to the lead frames while the power semiconductor element is sandwiched by the lead frames, wherein a metallic porous plating part is formed on a surface which faces the first electrode or the second electrode, the surface being a surface of at least one of the lead frames.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: April 28, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Norihito Tsukahara, Toshiyuki Kojima, Takayuki Hirose, Keiko Ikuta, Kohichi Tanda
  • Patent number: 8816481
    Abstract: A semiconductor device which can reduce a heat stress to a solder layer while suppressing an increase of thermal resistance is provided. A semiconductor device includes a semiconductor element, a solder layer which is arranged on at least one surface of the semiconductor element and a lead frame which is arranged on the solder layer so that a porous nickel plating part is sandwiched between the lead frame and the solder layer. Compared with a case that the semiconductor element and the lead frame are jointed by a solder directly, an increased part of a thermal resistance of the solder junction is held down only to a part of the porous nickel plating part and a thermal resistance applied to the solder layer can be reduced.
    Type: Grant
    Filed: October 1, 2012
    Date of Patent: August 26, 2014
    Assignee: Panasonic Corporation
    Inventors: Keiko Ikuta, Lianji Jin, Takayuki Hirose, Toshiyuki Kojima, Norihito Tsukahara, Kohichi Tanda
  • Publication number: 20140231981
    Abstract: A semiconductor device (1) includes: a semiconductor chip (2) having a first main surface and a second main surface opposite to the first main surface; a heat dissipating plate (3) opposed to the first main surface; a first electrode (5) disposed between the first main surface and the heat dissipating plate (3) so as to be electrically connected to the semiconductor chip (2); a pressure contact member (4) opposed to the second main surface; a second electrode (6) disposed between the second main surface and the pressure contact member (4) so as to be electrically connected to the semiconductor chip (2); and a pressure generating mechanism that generates a pressure for pressing the first electrode (5) into contact with the heat dissipating plate (3) and the semiconductor chip (2) and pressing the second electrode (6) into contact with the pressure contact member (4) and the semiconductor chip (2).
    Type: Application
    Filed: January 10, 2013
    Publication date: August 21, 2014
    Applicant: Panasonic Corporation
    Inventors: Toshiyuki Kojima, Tsukasa Shiraishi, Norihito Tsukahara, Takayuki Hirose, Keiko Ikuta, Masayoshi Koyama
  • Publication number: 20140110827
    Abstract: A pressed-contact type semiconductor device includes a power semiconductor element, on an upper surface of which at least a first electrode is formed and on a lower surface of which at least a second electrode is formed, lead frames which face the first electrode and the second electrode of the power semiconductor element respectively, and a clip which applies a pressure to the lead frames while the power semiconductor element is sandwiched by the lead frames, wherein a metallic porous plating part is formed on a surface which faces the first electrode or the second electrode, the surface being a surface of at least one of the lead frames.
    Type: Application
    Filed: October 19, 2012
    Publication date: April 24, 2014
    Applicant: Panasonic Corporation
    Inventors: Norihito Tsukahara, Toshiyuki Kojima, Takayuki Hirose, Keiko Ikuta, Kohichi Tanda
  • Publication number: 20140054170
    Abstract: A biosensor device which is possible to be downsized and potable, is free of the problem of solution outflow, and enables detection accurately and stably is realized.
    Type: Application
    Filed: February 17, 2012
    Publication date: February 27, 2014
    Inventors: Norihito Tsukahara, Keiko Ikuta, Akio Oki
  • Publication number: 20140054757
    Abstract: A semiconductor device which can reduce a heat stress to a solder layer while suppressing an increase of thermal resistance is provided. A semiconductor device includes a semiconductor element, a solder layer which is arranged on at least one surface of the semiconductor element and a lead frame which is arranged on the solder layer so that a porous nickel plating part is sandwiched between the lead frame and the solder layer. Compared with a case that the semiconductor element and the lead frame are jointed by a solder directly, an increased part of a thermal resistance of the solder junction is held down only to a part of the porous nickel plating part and a thermal resistance applied to the solder layer can be reduced.
    Type: Application
    Filed: October 1, 2012
    Publication date: February 27, 2014
    Applicant: Panasonic Corporation
    Inventors: Keiko Ikuta, Lianji Jin, Takayuki Hirose, Toshiyuki Kojima, Norihito Tsukahara, Kohichi Tanda