Patents by Inventor Keiko Morishita
Keiko Morishita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11579537Abstract: According to one embodiment, a pattern inspection method includes detecting a region of a photomask having a pattern that differs from a corresponding design, acquiring an exposure focus shift information including an exposure focus shift amount of a portion of a substrate corresponding to the detected region of the photomask. The exposure focus shift amount for the detected region is acquired from the exposure focus shift information, and then a pass/fail determination for the detected region is performed based on an estimated pattern to be formed on the substrate.Type: GrantFiled: February 24, 2021Date of Patent: February 14, 2023Assignee: Kioxia CorporationInventors: Keiko Morishita, Kosuke Takai
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Patent number: 11187975Abstract: A correction pattern generation device includes a processor configured to receive pattern information for a mask including a defect in a pattern formed on the mask, generate a correction pattern candidate for correcting the defect, calculate a correction difficulty degree for the correction pattern candidate, and select a correction pattern from correction pattern candidates based on the calculated correction difficulty degree for each correction pattern candidate if more than one correction pattern candidate for correcting the defect is generated.Type: GrantFiled: February 27, 2019Date of Patent: November 30, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventor: Keiko Morishita
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Publication number: 20210294225Abstract: According to one embodiment, a pattern inspection method includes detecting a region of a photomask having a pattern that differs from a corresponding design, acquiring an exposure focus shift information including an exposure focus shift amount of a portion of a substrate corresponding to the detected region of the photomask. The exposure focus shift amount for the detected region is acquired from the exposure focus shift information, and then a pass/fail determination for the detected region is performed based on an estimated pattern to be formed on the substrate.Type: ApplicationFiled: February 24, 2021Publication date: September 23, 2021Inventors: Keiko MORISHITA, Kosuke TAKAI
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Publication number: 20200089103Abstract: A correction pattern generation device includes a processor configured to receive pattern information for a mask including a defect in a pattern formed on the mask, generate a correction pattern candidate for correcting the defect, calculate a correction difficulty degree for the correction pattern candidate, and select a correction pattern from correction pattern candidates based on the calculated correction difficulty degree for each correction pattern candidate if more than one correction pattern candidate for correcting the defect is generated.Type: ApplicationFiled: February 27, 2019Publication date: March 19, 2020Inventor: Keiko Morishita
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Patent number: 10274821Abstract: A mask includes a plurality of line patterns provided on a substrate, the plurality of line patterns each including a line comprising a plurality of first layers and a plurality of second layers alternately stacked on the substrate. The lines of the plurality of line patterns extend in a first direction and the lines of the plurality of line patterns are spaced in a second direction crossing the first direction. A line of one of the plurality of line patterns has a first portion and a second portion on a side of the first portion in the first direction, the first portion wider than the second portion in the second direction.Type: GrantFiled: March 3, 2017Date of Patent: April 30, 2019Assignee: Toshiba Memory CorporationInventors: Keiko Morishita, Shingo Kanamitsu
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Patent number: 10241394Abstract: In a pattern formation method according to an embodiment, a resist pattern is formed on a first film formed on a substrate. In the process for forming the resist pattern, the resist pattern includes a first pattern including a defect in a predetermined region on the first film. Next, a second film is accumulated on the first pattern in the predetermined region. Furthermore, a second pattern is formed in the first film with the resist pattern and the second film. Then, a third pattern is formed in the predetermined region on the first film.Type: GrantFiled: September 8, 2015Date of Patent: March 26, 2019Assignee: Toshiba Memory CorporationInventors: Keiko Morishita, Shingo Kanamitsu, Hideaki Sakurai
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Publication number: 20170269471Abstract: A mask includes a plurality of line patterns provided on a substrate, the plurality of line patterns each including a line comprising a plurality of first layers and a plurality of second layers alternately stacked on the substrate. The lines of the plurality of line patterns extend in a first direction and the lines of the plurality of line patterns are spaced in a second direction crossing the first direction. A line of one of the plurality of line patterns has a first portion and a second portion on a side of the first portion in the first direction, the first portion wider than the second portion in the second direction.Type: ApplicationFiled: March 3, 2017Publication date: September 21, 2017Inventors: Keiko MORISHITA, Shingo KANAMITSU
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Publication number: 20160259240Abstract: In a pattern formation method according to an embodiment, a resist pattern is formed on a first film formed on a substrate. In the process for forming the resist pattern, the resist pattern includes a first pattern including a defect in a predetermined region on the first film. Next, a second film is accumulated on the first pattern in the predetermined region. Furthermore, a second pattern is formed in the first film with the resist pattern and the second film. Then, a third pattern is formed in the predetermined region on the first film.Type: ApplicationFiled: September 8, 2015Publication date: September 8, 2016Inventors: Keiko MORISHITA, Shingo KANAMITSU, Hideaki SAKURAI
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Patent number: 7947413Abstract: In a pattern evaluation method of determining whether a pattern formed on a photomask is acceptable, an aberration parameter of an image quality evaluation apparatus for determining a pattern image intensity in transferring a pattern formed on a photomask onto a wafer is acquired. An acceptance criterion value used in determining whether an abnormal pattern of the photomask including the effect of aberration of the image quality evaluation apparatus is acceptable is set through a lithographic simulation using the acquired aberration parameter. Then, using the image quality evaluation apparatus, an image intensity of the abnormal pattern of the photomask and an image intensity of a normal pattern corresponding to the abnormal pattern are obtained. It is determined whether the difference between the two acquired image intensities is within the set acceptance criterion value.Type: GrantFiled: October 8, 2008Date of Patent: May 24, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Keiko Morishita, Shingo Kanamitsu
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Publication number: 20090098472Abstract: In a pattern evaluation method of determining whether a pattern formed on a photomask is acceptable, an aberration parameter of an image quality evaluation apparatus for determining a pattern image intensity in transferring a pattern formed on a photomask onto a wafer is acquired. An acceptance criterion value used in determining whether an abnormal pattern of the photomask including the effect of aberration of the image quality evaluation apparatus is acceptable is set through a lithographic simulation using the acquired aberration parameter. Then, using the image quality evaluation apparatus, an image intensity of the abnormal pattern of the photomask and an image intensity of a normal pattern corresponding to the abnormal pattern are obtained. It is determined whether the difference between the two acquired image intensities is within the set acceptance criterion value.Type: ApplicationFiled: October 8, 2008Publication date: April 16, 2009Inventors: Keiko MORISHITA, Shingo Kanamitsu
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Patent number: 5469015Abstract: A vacuum microelectronic field-emission device includes: a substrate; an emitter portion formed to have at least an wedge portion extending in parallel to the substrate, the emitter portion being supported by the substrate; a gate portion formed a first given distance apart from the tip of the emitter portion, the gate portion being supported by the substrate, the gate portion being electrically insulated from the emitter portion; and a collector portion formed a second given distance apart from a tip of the emitter portion, the collector portion being supported by the substrate, the second given distance is equal to or larger than the first given distance, the collector portion being electrically insulated from the emitter portion and the gate portion.Type: GrantFiled: April 13, 1994Date of Patent: November 21, 1995Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Akira Kaneko, Toru Kanno, Keiko Morishita
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Patent number: 5343110Abstract: An electron emission element includes a substrate, a base electrode formed on the substrate, an emitter connecting portion formed on a part of the base electrode, and an emitter formed on the emitter connecting portion and having a wedge. The wedge of the emitter has a mesa shape in section. The wedge of the emitter has an upper surface and a lower surface which is wider than the upper surface. The wedge of the emitter has an edge provided with a lower corner of an acute angle in section. The electron emission element further includes an insulating layer formed on the substrate and spaced from the wedge of the emitter by a given gap, and a control electrode formed on the insulating layer for enabling electrons to be emitted from the edge of the emitter. The wedge of the emitter may have an inverted-mesa shape.Type: GrantFiled: June 2, 1992Date of Patent: August 30, 1994Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Akira Kaneko, Toru Kanno, Keiko Morishita
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Patent number: 5281891Abstract: An electron emission element includes an insulating substrate. A base electrode is formed on the insulating substrate. A plurality of emitters are formed on the base electrode and are arranged radially with respect to a given point. The emitters have wedge shapes with their respective tips facing inward. An insulating layer is formed on the substrate and the base electrode, and is spaced from the wedges of the emitters by given gaps. A control electrode is formed on the insulating layer for enabling electrons to be emitted from the tips of the wedge-shaped emitters.Type: GrantFiled: February 19, 1992Date of Patent: January 25, 1994Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Akira Kaneko, Toru Kanno, Keiko Morishita