Patents by Inventor Keiko Motokawa

Keiko Motokawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7313787
    Abstract: Different optimizing methods are applied in response to such a memory hierarchy to which a program mainly accesses when the program is executed. A memory hierarchy to which a program mainly accesses is designated by a user with employment of either a compiler option designation or a designation statement contained in the program. In a compiler, a memory hierarchy designation is analyzed, and an optimizing process according to the designated memory hierarchy is carried out.
    Type: Grant
    Filed: September 19, 2003
    Date of Patent: December 25, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Keiko Motokawa, Ichiro Kyushima, Shinichi Ito
  • Publication number: 20050144605
    Abstract: In an information processing system, a strip-mining process for a plurality of loops can be efficiently executed exactly intended by a user. A source program 206 includes strip-mining directives 401 and 402, which indicates a strip-mining applicable scope including two strip-mining target loops.
    Type: Application
    Filed: October 29, 2004
    Publication date: June 30, 2005
    Inventors: Keiko Motokawa, Shinichi Ito
  • Publication number: 20040199907
    Abstract: Different optimizing methods are applied in response to such a memory hierarchy to which a program mainly accesses when the program is executed. A memory hierarchy to which a program mainly accesses is designated by a user with employment of either a compiler option designation or a designation statement contained in the program. In a compiler, a memory hierarchy designation is analyzed, and an optimizing process according to the designated memory hierarchy is carried out.
    Type: Application
    Filed: September 19, 2003
    Publication date: October 7, 2004
    Applicant: Hitachi, Ltd.
    Inventors: Keiko Motokawa, Ichiro Kyushima, Shinichi Ito
  • Patent number: 6401187
    Abstract: The present invention provides a memory access optimizing method which judges an access method suitable for each of memory accesses and executes the preload optimization and prefetch optimization, according to the judgement result, for an architecture equipped with a prefetch mechanism to write the data on a main storage device into a cache memory and a preload mechanism to write the data on the main storage device into a register without writing it into the cache memory. The memory access method judging step analyzes whether or not there is a designation of a memory access method by a user. Moreover, the memory access method judging step investigates whether or not the data are already in a cache memory, whether or not the data compete with other data for a cache, whether or not the data are to be referred to again later, and whether or not the data fulfill the restriction on register resources.
    Type: Grant
    Filed: June 12, 2000
    Date of Patent: June 4, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Keiko Motokawa, Hiroyasu Nishiyama, Sumio Kikuchi
  • Publication number: 20010044930
    Abstract: The present invention provides a loop optimization method and a compiler suitable for improving the execution time of a loop including assumed-shape array. A loop optimizer detects the outermost loop included in a subroutine, then traverse every statements in the outermost loop (including any inner nested loops) to detect array reference to the assumed-shape arrays to register thus detected assumed-shape arrays to the assumed-shape array table. Then for thus registered assumed-shape arrays, the optimizer generates a conditional expression determining whether the first order dimension stride of each array is 1 or not, to form a conditional statement by concatenating the conditional expressions of every elements registered to the assumed-shape array table with the conditional “AND” and then duplicates the loop by copying the outer loop and the loop body entirely in focus at that time to the part to be executed when the condition is TRUE and to the part to be executed when the condition is FALSE.
    Type: Application
    Filed: January 18, 2001
    Publication date: November 22, 2001
    Applicant: Hitachi, Ltd.
    Inventors: Kenichi Miyata, Keiko Motokawa