Abstract: Cross reference information is generated when comparing between a logic circuit and a layout in order to facilitate retrieval of optimum corresponding information of logic circuit and layout. A design verification apparatus includes a storage unit which stores logic circuit data and layout data on its layout pattern; an element recognition unit which recognizes the connection relation of elements, and a comparative verification unit. The comparative verification unit compares and verifies the correspondence between the connection relation of logic circuit and connection relation of layout based on the logic circuit data to merge elements of the logic circuit, and compares and verifies the correspondence of the connection relation of the merged elements. Further, the apparatus generates a cross reference information file specifying the corresponding relation of the elements and their wiring in first and second function units depending on the connection relation of the logic circuit.