Patents by Inventor Keiko Yamaguchi

Keiko Yamaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090154370
    Abstract: When a processing delay detection unit (27) detects that an end timing (F) of measurement of the reception quality of a common pilot signal transmitted from a wireless base station has delayed from a creation start time limit for reception quality information, approximate reception quality information (k) is created on the basis of reception quality measured before the creation start time limit. The approximate reception quality information is transmitted to a wireless base station. The delay of the transmission timing of the reception quality information can be prevented, and the wireless base station can quickly set the transmission rate of transmission data to a cellular phone.
    Type: Application
    Filed: April 27, 2007
    Publication date: June 18, 2009
    Inventor: Keiko Yamaguchi
  • Publication number: 20080248502
    Abstract: The inventors discovered that the adhesion molecule CAR, known to be localized in intracellular adhesion sites, functioned as an adhesion molecule for activated lymphocytes. Further, the inventors identified CARL, a novel CAR ligand expressed in lymphocytes, and clarified that the ligand was expressed selectively in Th1 cells. In addition, they found that anti-CAR antibodies could inhibit the adhesion of activated lymphocytes to CAR molecules. Thus, the present invention provides methods for detecting Th1 cells using CAR or anti-CARL antibodies, and methods of screening for inhibitors suppressing the adhesion of Th1 cells using the binding between CAR and CARL as an index. Furthermore, the present invention relates to methods of screening for inhibitors of the binding between CAR and CARL, antibodies that inhibit the binding between CAR and CARL, and therapeutic compositions comprising these antibodies.
    Type: Application
    Filed: April 28, 2005
    Publication date: October 9, 2008
    Applicant: EISAI R&D MANAGEMENT CO., LTD.
    Inventors: Keiko Yamaguchi, Toshio Imai, Kenzo Muramoto
  • Publication number: 20070280982
    Abstract: The invention features anti-microbial compositions comprising compositions of hop acid alkali metal salts and alkaline earth metal salts and methods of using them to inhibit microbial growth.
    Type: Application
    Filed: March 29, 2007
    Publication date: December 6, 2007
    Inventors: Mitsunori Ono, Keiko Yamaguchi, Naoto Yamaguchi
  • Publication number: 20070122845
    Abstract: The present invention provides methods for identifying a GPR83 agonist capable of stimulating a regulatory T cell function and methods for identifying a GPR83 antagonist capable of suppressing a regulatory T cell function.
    Type: Application
    Filed: September 15, 2006
    Publication date: May 31, 2007
    Applicant: Eisai R&D Management Co., Ltd.
    Inventors: Tetsu Kawano, Junro Kuromitsu, Akiko Hamaguchi, Keiko Yamaguchi, Takashi Seiki, Kazuma Takase
  • Patent number: 6720200
    Abstract: Using a mask opening a gate region, an undoped GaAs layer is selectively etched with respect to an undoped Al0.2Ga0.8As layer by dry etching with introducing a mixture gas of a chloride gas containing only chlorine and a fluoride gas containing only fluorine (e.g. BCl3+SF6 or so forth). By about 100% over-etching is performed for the undoped GaAs layer, etching (side etching) propagates in transverse direction of the undoped GaAs layer. With using the mask, a gate electrode of WSi is formed. Thus, a gap in a width of about 20 nm is formed by etching in the transverse direction on the drain side of the gate electrode. By this, a hetero junction FET having reduced fluctuation of characteristics of an FET, such as a threshold value, lower a rising voltage and higher breakdown characteristics.
    Type: Grant
    Filed: May 22, 2001
    Date of Patent: April 13, 2004
    Assignee: NEC Corporation
    Inventors: Keiko Yamaguchi, Naotaka Iwata
  • Patent number: 6426523
    Abstract: Using a mask opening a gate region, an undoped GaAs layer is selectively etched with respect to an undoped Al0.2Ga0.8As layer by dry etching with introducing a mixture gas of a chloride gas containing only chlorine and a fluoride gas containing only fluorine (e.g. BCl3+SF6 or so forth). By about 100% over-etching is performed for the undoped GaAs layer, etching (side etching) propagates in transverse direction of the undoped GaAs layer. With using the mask, a gate electrode of WSi is formed. Thus, a gap in a width of about 20 nm is formed by etching in the transverse direction on the drain side of the gate electrode. By this, a hetero junction FET having reduced fluctuation of characteristics of an FET, such as a threshold value, lower rising voltage and higher breakdown characteristics is obtained.
    Type: Grant
    Filed: October 27, 1997
    Date of Patent: July 30, 2002
    Assignee: NEC Corporation
    Inventors: Keiko Yamaguchi, Naotaka Iwata
  • Publication number: 20010024846
    Abstract: Using a mask opening a gate region, an undoped GaAs layer is selectively etched with respect to an undoped Al0.2Ga0.8As layer by dry etching with introducing a mixture gas of a chloride gas containing only chlorine and a fluoride gas containing only fluorine (e.g. BCl3+SF6 or so forth). By about 100% over-etching is performed for the undoped GaAs layer, etching (side etching) propagates in transverse direction of the undoped GaAs layer. With using the mask, a gate electrode of WSi is formed. Thus, a gap in a width of about 20 nm is formed by etching in the transverse direction on the drain side of the gate electrode. By this, a hetero junction FET having reduced fluctuation of characteristics of an FET, such as a threshold value, lower a rising voltage and higher breakdown characteristics.
    Type: Application
    Filed: May 22, 2001
    Publication date: September 27, 2001
    Inventors: Keiko Yamaguchi, Naotaka Iwata
  • Patent number: 6130589
    Abstract: A matching circuit is formed by a series inductor, a parallel capacitor, a drain bias circuit, and a DC-blocking capacitor for the purpose of impedance matching. A capacitor having a capacitance that is dependent upon the bias voltage is used as the parallel capacitor. This can be, for example, a material such as a (Ba.sub.X Sr.sub.1-X)TiO.sub.3 thin-film, which exhibits a capacitance having a bias voltage dependency. Because this thin-film capacitor exhibits polarization by an electrical field, its capacitance is the largest with a bias of 0 volts, and is reduced to approximately 50% as the bias voltage is increased. By using this capacitor in a matching circuit, it is possible to change the matching condition as the output power is increased, that is, as the voltage applied to the capacitor is increased.
    Type: Grant
    Filed: June 4, 1998
    Date of Patent: October 10, 2000
    Assignee: NEC Corporation
    Inventors: Keiko Yamaguchi, Naotaka Iwata
  • Patent number: 6072205
    Abstract: A passive element circuit is formed by a spiral inductor, a high-dielectric-constant thin-film capacitor, a via hole, and a bonding pad. By using SrTiO.sub.3 as the high-dielectric-constant thin-film, which exhibits a dielectric constant of 200 up to a frequency of 20 GHz, it is possible to achieve a reduction of the capacitor surface area to approximately 1/30 of the area formerly required when using a SiN.sub.x (dielectric constant up to 6.5). Two high-dielectric-constant thin-film capacitors, a via hole for grounding, and a bonding pad are disposed at the center, which are surrounded by the spiral inductor. To connect the two high-dielectric-constant thin-film capacitors are joined in series, they are formed on one high-dielectric-constant thin-film. A lead from the spiral inductor is made by a metal wire from the bonding pad at the center.
    Type: Grant
    Filed: June 4, 1998
    Date of Patent: June 6, 2000
    Assignee: NEC Corporation
    Inventors: Keiko Yamaguchi, Naotaka Iwata