Abstract: A memory access control system which performs a DMA transfer and allows a central control unit to perform a specific, required software operation. A central control unit sets a flag after running the specific software operation. The DMA transfer includes a first phase and a second phase, the first phase being a first transfer between a main memory and a first buffer memory and then a successive, second transfer between the main memory and a second buffer memory. The second phase is a transfer between a respective buffer memory and an external memory. A first DMA controller requests the first phase and controls the transfer of the second phase from a respective buffer memory when a transfer of the first phase from the main memory to the respective buffer memory ends, and prohibits a request for the first phase when the first transfer ends during a transfer of the second phase from the second buffer memory.