Patents by Inventor Keimei Masamoto

Keimei Masamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11742461
    Abstract: A semiconductor device includes: a mounting board; and a semiconductor element disposed on the mounting board via metal bumps, wherein the semiconductor element includes a semiconductor stacked structure and first electrodes, the mounting board includes second electrodes, the metal bumps include a second layer in contact with the second electrodes of the semiconductor element and a first layer located on a side opposite to the second electrodes, an average crystal grain size of crystals included in the second layer is larger than an average crystal grain size of crystals included in the first layer, and the first layer is spaced apart from the second electrodes of the semiconductor element.
    Type: Grant
    Filed: July 8, 2022
    Date of Patent: August 29, 2023
    Assignee: NUVOTON TECHNOLOGY CORPORATION JAPAN
    Inventors: Masanori Hiroki, Shigeo Hayashi, Kenji Nakashima, Toshiya Fukuhisa, Keimei Masamoto, Atsushi Yamada
  • Publication number: 20230146321
    Abstract: A semiconductor device includes: a first electrode provided on a semiconductor multilayer structure; a second electrode provided on a substrate; and a bonding metal layer which bonds the first electrode and the second electrode together. The bonding metal layer includes a gap inside.
    Type: Application
    Filed: December 30, 2022
    Publication date: May 11, 2023
    Inventors: Mitsuaki OYA, Masanori HIROKI, Keimei MASAMOTO, Shigeo HAYASHI
  • Patent number: 11569424
    Abstract: A semiconductor device includes: a first electrode provided on a semiconductor multilayer structure; a second electrode provided on a substrate; and a bonding metal layer which bonds the first electrode and the second electrode together. The bonding metal layer includes a gap inside.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: January 31, 2023
    Assignee: NUVOTON TECHNOLOGY CORPORATION JAPAN
    Inventors: Mitsuaki Oya, Masanori Hiroki, Keimei Masamoto, Shigeo Hayashi
  • Publication number: 20220344547
    Abstract: A semiconductor device includes: a mounting board; and a semiconductor element disposed on the mounting board via metal bumps, wherein the semiconductor element includes a semiconductor stacked structure and first electrodes, the mounting board includes second electrodes, the metal bumps include a second layer in contact with the second electrodes of the semiconductor element and a first layer located on a side opposite to the second electrodes, an average crystal grain size of crystals included in the second layer is larger than an average crystal grain size of crystals included in the first layer, and the first layer is spaced apart from the second electrodes of the semiconductor element.
    Type: Application
    Filed: July 8, 2022
    Publication date: October 27, 2022
    Inventors: Masanori HIROKI, Shigeo HAYASHI, Kenji NAKASHIMA, Toshiya FUKUHISA, Keimei MASAMOTO, Atsushi YAMADA
  • Patent number: 11417805
    Abstract: A semiconductor device includes: a mounting board; and a semiconductor element disposed on the mounting board via metal bumps, wherein the semiconductor element includes a semiconductor stacked structure and first electrodes, the mounting board includes second electrodes, the metal bumps include a first layer in contact with the first electrodes of the semiconductor element and a second layer located on a side opposite to the first electrodes, an average crystal grain size of crystals included in the first layer is larger than an average crystal grain size of crystals included in the second layer, and the second layer is spaced apart from the first electrodes of the semiconductor element.
    Type: Grant
    Filed: October 20, 2021
    Date of Patent: August 16, 2022
    Assignee: NUVOTON TECHNOLOGY CORPORATION JAPAN
    Inventors: Masanori Hiroki, Shigeo Hayashi, Kenji Nakashima, Toshiya Fukuhisa, Keimei Masamoto, Atsushi Yamada
  • Publication number: 20220085244
    Abstract: A semiconductor light-emitting element includes: a semiconductor layer; an electrode disposed on the semiconductor layer, the electrode including a power feeding portion and an extension portion extending from the power feeding portion. The power feeding portion has a width greater than a width of the extension portion. The electrode includes an electrode layer and a wiring layer. The electrode layer includes a first metal layer disposed in the power feeding portion, and a second metal layer disposed closer to an extension portion side than the first metal layer is and directly connected to the first metal layer. The first metal layer and the second metal layer are in ohmic contact with the semiconductor layer. The first metal layer has an electrical conductivity higher than an electrical conductivity of the second metal layer. The wiring layer is continuously disposed on the first metal layer and the second metal layer.
    Type: Application
    Filed: November 29, 2021
    Publication date: March 17, 2022
    Inventors: Keimei MASAMOTO, Mitsuaki OYA, Shigeo HAYASHI, Masanori HIROKI, Masahiro KUME, Gaku NISHIKAWA
  • Publication number: 20220052231
    Abstract: A semiconductor device includes: a mounting board; and a semiconductor element disposed on the mounting board via metal bumps, wherein the semiconductor element includes a semiconductor stacked structure and first electrodes, the mounting board includes second electrodes, the metal bumps include a first layer in contact with the first electrodes of the semiconductor element and a second layer located on a side opposite to the first electrodes, an average crystal grain size of crystals included in the first layer is larger than an average crystal grain size of crystals included in the second layer, and the second layer is spaced apart from the first electrodes of the semiconductor element.
    Type: Application
    Filed: October 20, 2021
    Publication date: February 17, 2022
    Inventors: Masanori HIROKI, Shigeo HAYASHI, Kenji NAKASHIMA, Toshiya FUKUHISA, Keimei MASAMOTO, Atsushi YAMADA
  • Patent number: 11183615
    Abstract: A semiconductor device includes: a mounting board; and a semiconductor element disposed on the mounting board via metal bumps, wherein the semiconductor element includes a semiconductor stacked structure and first electrodes, the mounting board includes second electrodes, the metal bumps include a first layer in contact with the first electrodes of the semiconductor element and a second layer located on a side opposite to the first electrodes, an average crystal grain size of crystals included in the first layer is larger than an average crystal grain size of crystals included in the second layer, and the second layer is spaced apart from the first electrodes of the semiconductor element.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: November 23, 2021
    Assignee: NUVOTON TECHNOLOGY CORPORATION JAPAN
    Inventors: Masanori Hiroki, Shigeo Hayashi, Kenji Nakashima, Toshiya Fukuhisa, Keimei Masamoto, Atsushi Yamada
  • Publication number: 20210217942
    Abstract: A semiconductor light emitting element includes: a substrate; an n-type layer; a light emitting layer; a p-type layer; a p electrode located above the p-type layer; an n electrode located in a region that is above the n-type layer and in which the light emitting layer and the p-type layer are not located; a p-electrode bump connected to the p electrode; an n-electrode bump connected to the n electrode; and an insulation bump located in at least one of a region between the n-electrode bump and the p-type layer and a region whose distance from an end of the p-type layer closer to the n-electrode bump is shorter than a distance from the end to the p-electrode bump, in a plan view of the substrate. A surface of the insulation bump opposite to a surface facing the substrate is insulated from the p electrode and the n electrode.
    Type: Application
    Filed: March 10, 2021
    Publication date: July 15, 2021
    Inventors: Yasumitsu KUNOH, Masahiro KUME, Masanori HIROKI, Keimei MASAMOTO, Toshiya FUKUHISA, Shigeo HAYASHI
  • Publication number: 20210104652
    Abstract: A semiconductor device includes: a first electrode provided on a semiconductor multilayer structure; a second electrode provided on a substrate; and a bonding metal layer which bonds the first electrode and the second electrode together. The bonding metal layer includes a gap inside.
    Type: Application
    Filed: December 15, 2020
    Publication date: April 8, 2021
    Inventors: Mitsuaki OYA, Masanori HIROKI, Keimei MASAMOTO, Shigeo HAYASHI
  • Publication number: 20200365771
    Abstract: A semiconductor device includes: a mounting board; and a semiconductor element disposed on the mounting board via metal bumps, wherein the semiconductor element includes a semiconductor stacked structure and first electrodes, the mounting board includes second electrodes, the metal bumps include a first layer in contact with the first electrodes of the semiconductor element and a second layer located on a side opposite to the first electrodes, an average crystal grain size of crystals included in the first layer is larger than an average crystal grain size of crystals included in the second layer, and the second layer is spaced apart from the first electrodes of the semiconductor element.
    Type: Application
    Filed: December 20, 2018
    Publication date: November 19, 2020
    Applicants: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD., PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
    Inventors: Masanori HIROKI, Shigeo HAYASHI, Kenji NAKASHIMA, Toshiya FUKUHISA, Keimei MASAMOTO, Atsushi YAMADA
  • Publication number: 20150037917
    Abstract: In a system light-emitting device, a nitride semiconductor layer including a light-emitting layer is stacked on an optically transmissive substrate, and a reflective electrode including an Ag layer is stacked on the semiconductor layer. As annealing, a first annealing step that is a preceding step and a second annealing step that is a succeeding step are performed. In the first annealing step, the annealing is performed using inert gas of nitrogen gas as ambient gas. In the second annealing step, the annealing is performed using gas including oxygen gas as ambient gas. The two-stages of the annealing are performed, whereby occurrence of wrinkles on the Ag layer can be reduced, and surface roughness can be reduced.
    Type: Application
    Filed: April 19, 2013
    Publication date: February 5, 2015
    Inventors: Atsuhiro Hori, Keimei Masamoto