Patents by Inventor Kein Fee Liew

Kein Fee Liew has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • BACKSIDE MOLD PROCESS FOR ULTRA THIN SUBSTRATE AND PACKAGE ON PACKAGE ASSEMBLY
    Publication number: 20150072474
    Abstract: In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, forming a stiffening mold on a backside of the coreless substrate strip adjacent to sites where solder balls are to be attached, and attaching solder balls to the backside of the coreless substrate strip amongst the stiffening mold. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: September 15, 2014
    Publication date: March 12, 2015
    Inventors: Huay Huay Sim, Choong Kooi Chee, Kein Fee Liew
  • Backside mold process for ultra thin substrate and package on package assembly
    Patent number: 8835220
    Abstract: In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, forming a stiffening mold on a backside of the coreless substrate strip adjacent to sites where solder balls are to be attached, and attaching solder balls to the backside of the coreless substrate strip amongst the stiffening mold. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: September 16, 2014
    Assignee: Intel Corporation
    Inventors: Huay Huay Sim, Choong Kooi Chee, Kein Fee Liew
  • BACKSIDE MOLD PROCESS FOR ULTRA THIN SUBSTRATE AND PACKAGE ON PACKAGE ASSEMBLY
    Publication number: 20130230946
    Abstract: In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, forming a stiffening mold on a backside of the coreless substrate strip adjacent to sites where solder balls are to be attached, and attaching solder balls to the backside of the coreless substrate strip amongst the stiffening mold. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: February 25, 2013
    Publication date: September 5, 2013
    Inventors: Huay Huay Sim, Choong Kooi Chee, Kein Fee Liew
  • Backside mold process for ultra thin substrate and package on package assembly
    Patent number: 8384223
    Abstract: In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, forming a stiffening mold on a backside of the coreless substrate strip adjacent to sites where solder balls are to be attached, and attaching solder balls to the backside of the coreless substrate strip amongst the stiffening mold. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: February 26, 2013
    Assignee: Intel Corporation
    Inventors: Huay Huay Sim, Choong Kooi Chee, Kein Fee Liew
  • BACKSIDE MOLD PROCESS FOR ULTRA THIN SUBSTRATE AND PACKAGE ON PACKAGE ASSEMBLY
    Publication number: 20090321949
    Abstract: In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, forming a stiffening mold on a backside of the coreless substrate strip adjacent to sites where solder balls are to be attached, and attaching solder balls to the backside of the coreless substrate strip amongst the stiffening mold. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: June 30, 2008
    Publication date: December 31, 2009
    Inventors: Huay Huay Sim, Choong Kooi Chee, Kein Fee Liew