Patents by Inventor Keiri Nakanishi
Keiri Nakanishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11609844Abstract: A memory system includes a first memory that is nonvolatile, a second memory that is volatile, and a memory controller. The memory controller is configured to store first information in the second memory. The first information includes management information. The memory controller is further configured to compress the first information. The compressed first information is second information. The memory controller is configured to store the second information in the first memory.Type: GrantFiled: March 2, 2020Date of Patent: March 21, 2023Assignee: KIOXIA CORPORATIONInventors: Keiri Nakanishi, Konosuke Watanabe, Kohei Oikawa, Daisuke Iwai
-
Publication number: 20230081961Abstract: According to one embodiment, a compression circuit generates substrings from input data for (3+M) cycles, the input data being N bytes per cycle, a byte length of each substring being greater than or equal to (NĂ—(1+M)+1); obtains a set of matches, each of the matches including at least one past input data which input past and corresponds to at least a part of each of the substrings; selects a subset of matches from the set of matches including the input data of one cycle; and outputs the subset of matches. M is zero or a natural number. N is a positive integer which is two or more.Type: ApplicationFiled: March 14, 2022Publication date: March 16, 2023Applicant: Kioxia CorporationInventors: Sho KODAMA, Keiri NAKANISHI, Daisuke YASHIMA
-
Publication number: 20230070623Abstract: According to one embodiment, a data compression device includes a dictionary match determination unit, an extended matching generator, a match selector and a match connector. The dictionary match determination unit searches for first past input data matching first new input data. The extended matching generator compares second past input data subsequent to the first past input data with second new input data subsequent to the first new input data. The match selector generates compressed data by replacing a part of the input data with match information output from the dictionary match determination unit or the extended matching generator. The match connector replaces a plurality of match information in the compressed data with single match information.Type: ApplicationFiled: March 4, 2022Publication date: March 9, 2023Applicant: Kioxia CorporationInventors: Daisuke YASHIMA, Youhei FUKAZAWA, Sho KODAMA, Keiri NAKANISHI, Masato SUMIYOSHI, Kohei OIKAWA, Zheye WANG, Takashi MIURA
-
Patent number: 11593286Abstract: According to one embodiment, a memory system includes a first compression unit, a second compression unit, a non-volatile memory, a first decoding unit, a conversion unit and an output unit. The first compression unit is configured to output second data obtained by compressing first data. The second compression unit is configured to output third data obtained by compressing the second data. Fourth data based on the third data is written to the non-volatile memory. The first decoding unit is configured to decode the third data based on the fourth data to the second data. The conversion unit is configured to acquire fifth data by converting a format of the second data. The output unit is configured to output the fifth data to a host.Type: GrantFiled: June 11, 2021Date of Patent: February 28, 2023Assignee: Kioxia CorporationInventors: Keiri Nakanishi, Kazuhiro Hiwada, Youhei Fukazawa
-
Patent number: 11588498Abstract: According to one embodiment, a buffer stores first hash values and first complementary data. A first conversion unit converts consecutive characters in a second character string into second hash values and second complementary data. A search unit searches for consecutive first hash values from the buffer, and output a pointer. A selection unit selects consecutive first hash values and pieces of first complementary data from the buffer. A second conversion unit converts the consecutive first hash values into a third character string using the pieces of first complementary data. A comparison unit compares the second character string with the third character string to acquire a matching length. An output unit output the matching length with the pointer.Type: GrantFiled: September 10, 2021Date of Patent: February 21, 2023Assignee: Kioxia CorporationInventors: Daisuke Yashima, Kohei Oikawa, Sho Kodama, Keiri Nakanishi, Masato Sumiyoshi, Youhei Fukazawa, Zheye Wang, Takashi Miura
-
Patent number: 11561738Abstract: A memory system includes a storage device and a memory controller. The memory controller includes an encoder and a decoder. The encoder includes a first code table updating section configured to update the encoding code table and an encoding flow controlling section configured to control input to the first code table updating section by using a first data amount indicating a data amount of the input symbol. The first data amount is calculated based on the input symbol. The decoder includes a second code table updating section configured to update the decoding code table and a decoding flow controlling section configured to control input to the second code table updating section by using a second data amount indicating a data amount of the output symbol. The second data amount is calculated based on the output symbol in the same way as the calculation of the first data amount.Type: GrantFiled: March 4, 2021Date of Patent: January 24, 2023Assignee: Kioxia CorporationInventors: Masato Sumiyoshi, Keiri Nakanishi, Sho Kodama, Kohei Oikawa
-
Publication number: 20230006689Abstract: According to one embodiment, an interleaving unit divides a symbol string into first and second symbols. A first coding unit converts the first symbols to first codewords. A first packet generating unit generates first packets including the first codewords. A first request generating unit generates first packet requests including sizes of variable length packets. A second coding unit converts the second symbols to second codewords. A second packet generating unit generates second packets including the second codewords. A second request generating unit generates second packet requests including sizes of variable length packets. A multiplexer outputs a compressed stream including the first and second variable length packets cut out from the first and second packets.Type: ApplicationFiled: March 7, 2022Publication date: January 5, 2023Inventors: Masato SUMIYOSHI, Keiri NAKANISHI, Kohei OIKAWA, Sho KODAMA
-
Publication number: 20220398019Abstract: A compression device includes an analyzer circuit, a control circuit, a compressor circuit, and a selector circuit. The analyzer circuit is configured to analyze first data that is input thereto and generate one or more parameter values regarding data compression and/or decompression. The control circuit is configured to generate at least one compression mode information indicating whether or not compression is to be performed, based on the one or more parameter values. The compressor circuit is configured to compress the first data into second data according to the compression mode information. The selector circuit is configured to output the first data if not compressed or the second data if the first data is compressed, together with the compression mode information.Type: ApplicationFiled: March 3, 2022Publication date: December 15, 2022Inventors: Youhei FUKAZAWA, Sho KODAMA, Keiri NAKANISHI, Kohei OIKAWA, Takashi MIURA, Daisuke YASHIMA, Masato SUMIYOSHI, Zheye WANG
-
Publication number: 20220353519Abstract: According to one embodiment, a memory system includes a frequency value update unit, a first intra-group rearranging unit, a second intra-group rearranging unit, and a routing unit. The frequency value update unit adds a first value to each of one or more first frequency values that are associated with one or more first symbols, respectively, in one or more entries in a table. The first intra-group rearranging unit rearranges first entries, which belong to a first group, using frequency values in the first entries. The second intra-group rearranging unit rearranges second entries, which belong to a second group lower than the first group, using frequency values. The routing unit rearranges at least one of the first entries and at least one of the second entries.Type: ApplicationFiled: July 19, 2022Publication date: November 3, 2022Applicant: Kioxia CorporationInventors: Daisuke YASHIMA, Masato SUMIYOSHI, Keiri NAKANISHI, Takashi MIURA, Kohei OIKAWA, Sho KODAMA, Youhei FUKAZAWA, Zheye WANG
-
Patent number: 11461008Abstract: A memory system including a history buffer, a hash calculator, a read pointer table, a history buffer writing circuit, a read pointer writing circuit, a read pointer reading circuit, a history buffer reading circuit, a matching circuit replacing the input data string with a reference information referring the matching candidate data string in the case where at least a part of the input data string and a part of the matching candidate data string match. Reading of the read pointer by the read pointer reading circuit and reading of the stored input data string by the history buffer reading circuit are executed after writing of the read pointer by the read pointer writing circuit and writing of the input data string by the history buffer writing circuit are finished.Type: GrantFiled: August 20, 2020Date of Patent: October 4, 2022Assignee: Kioxia CorporationInventors: Sho Kodama, Keiri Nakanishi, Kohei Oikawa, Daisuke Yashima, Masato Sumiyoshi, Youhei Fukazawa
-
Publication number: 20220294469Abstract: According to one embodiment, a compression device includes a coding information generation unit. The unit determines code lengths that are respectively associated with a plurality of symbols, based on a frequency of occurrence of each of the plurality of symbols. When the plurality of symbols include one or more first symbols that are respectively associated with one or more first code lengths exceeding an upper limit, the unit changes the first code lengths to the upper limit, selects, from one or more second symbols of the plurality of symbols that are respectively associated with one or more second code lengths shorter than the upper limit, at least one symbol in descending associated code length order, changes at least one code length associated with the symbol to the upper limit.Type: ApplicationFiled: June 15, 2021Publication date: September 15, 2022Applicant: Kioxia CorporationInventors: Sho KODAMA, Masato SUMIYOSHI, Keiri NAKANISHI
-
Patent number: 11431995Abstract: According to one embodiment, a memory system includes a frequency value update unit, a first intra-group rearranging unit, a second intra-group rearranging unit, and a routing unit. The frequency value update unit adds a first value to each of one or more first frequency values that are associated with one or more first symbols, respectively, in one or more entries in a table. The first intra-group rearranging unit rearranges first entries, which belong to a first group, using frequency values in the first entries. The second intra-group rearranging unit rearranges second entries, which belong to a second group lower than the first group, using frequency values. The routing unit rearranges at least one of the first entries and at least one of the second entries.Type: GrantFiled: September 14, 2020Date of Patent: August 30, 2022Assignee: Kioxia CorporationInventors: Daisuke Yashima, Masato Sumiyoshi, Keiri Nakanishi, Takashi Miura, Kohei Oikawa, Sho Kodama, Youhei Fukazawa, Zheye Wang
-
Publication number: 20220269416Abstract: According to one embodiment, a memory system includes a compressor configured to output second data obtained by compressing input first data and a non-volatile memory to which third data based on the second data output from the compressor is written. The compressor includes a dictionary coding unit configured to perform dictionary coding on the first data, an entropy coding unit configured to perform entropy coding on the result of the dictionary coding, a first calculation unit configured to calculate compression efficiencies of the dictionary coding and the entropy coding, and a first control unit configured to control an operation of at least one of the dictionary coding unit and the entropy coding unit based on the compression efficiencies and a power reduction level.Type: ApplicationFiled: June 14, 2021Publication date: August 25, 2022Applicant: Kioxia CorporationInventors: Sho KODAMA, Keiri NAKANISHI, Masato SUMIYOSHI, Zheye WANG, Kohei OIKAWA, Youhei FUKAZAWA, Daisuke YASHIMA, Takashi MIURA
-
Publication number: 20220255556Abstract: According to one embodiment, a buffer stores first hash values and first complementary data. A first conversion unit converts consecutive characters in a second character string into second hash values and second complementary data. A search unit searches for consecutive first hash values from the buffer, and output a pointer. A selection unit selects consecutive first hash values and pieces of first complementary data from the buffer. A second conversion unit converts the consecutive first hash values into a third character string using the pieces of first complementary data. A comparison unit compares the second character string with the third character string to acquire a matching length. An output unit output the matching length with the pointer.Type: ApplicationFiled: September 10, 2021Publication date: August 11, 2022Inventors: Daisuke YASHIMA, Kohei OIKAWA, Sho KODAMA, Keiri NAKANISHI, Masato SUMIYOSHI, Youhei FUKAZAWA, Zheye WANG, Takashi MIURA
-
Patent number: 11397546Abstract: A memory system including a storage device and a memory controller controlling the storage device and decoding an encoded data. The memory controller including: a history buffer storing a decoded data string; a history buffer read controller executing a read request to the history buffer; a decode executing section generating a first shaped data string based on the decoded data string read from the history buffer, generating a second shaped data string by referring the first shaped data string before the first shaped data string being written back to the history buffer in response to the read request, and generating a decoded result using the first shaped data string and the second shaped data string.Type: GrantFiled: July 29, 2020Date of Patent: July 26, 2022Assignee: Kioxia CorporationInventors: Masato Sumiyoshi, Keiri Nakanishi, Takashi Miura, Kohei Oikawa, Daisuke Yashima, Sho Kodama, Youhei Fukazawa, Zheye Wang
-
Publication number: 20220187994Abstract: According to one embodiment, a compression device includes a first storage unit, a second storage unit, a calculation unit, and a comparison unit. The first storage unit stores addresses associated with hash values, respectively. The second storage unit includes storage areas specified by the addresses, respectively. The calculation unit determines a hash function to be used for first data in accordance with at least a part of the first data, and calculates a hash value using the hash function and at least a part of second data included in the first data. The comparison unit acquires third data from a storage area in the second storage unit specified by a first address, and compares the second data with the third data. The first address is stored in the first storage unit and is associated with the hash value.Type: ApplicationFiled: September 9, 2021Publication date: June 16, 2022Inventors: Youhei FUKAZAWA, Kohei OIKAWA, Sho KODAMA, Keiri NAKANISHI, Takashi MIURA, Daisuke YASHIMA, Masato SUMIYOSHI, Zheye WANG
-
Publication number: 20220171724Abstract: According to one embodiment, a memory system includes a first compression unit, a second compression unit, a non-volatile memory, a first decoding unit, a conversion unit and an output unit. The first compression unit is configured to output second data obtained by compressing first data. The second compression unit is configured to output third data obtained by compressing the second data. Fourth data based on the third data is written to the non-volatile memory. The first decoding unit is configured to decode the third data based on the fourth data to the second data. The conversion unit is configured to acquire fifth data by converting a format of the second data. The output unit is configured to output the fifth data to a host.Type: ApplicationFiled: June 11, 2021Publication date: June 2, 2022Applicant: Kioxia CorporationInventors: Keiri NAKANISHI, Kazuhiro HIWADA, Youhei FUKAZAWA
-
Patent number: 11309909Abstract: A compression device includes a dictionary based encoder, a second buffer, a comparator, and a compression data generator. The dictionary based encoder searches for second data at least partially matching first data from a first buffer, and acquires a first match position indicating a position of the second data in the first buffer and a match length indicating a matched length of the first and second data. The second buffer stores the previously acquired second match position with an index. The compression data generator generates first compressed data that includes the index assigned to the second match position in the second buffer and the match length when the first match position matches the second match position in the second buffer.Type: GrantFiled: September 2, 2020Date of Patent: April 19, 2022Assignee: Kioxia CorporationInventors: Youhei Fukazawa, Keiri Nakanishi, Sho Kodama, Masato Sumiyoshi, Kohei Oikawa, Daisuke Yashima, Takashi Miura, Zheye Wang
-
Publication number: 20220083282Abstract: A memory system includes a storage device and a memory controller. The memory controller includes an encoder and a decoder. The encoder includes a first code table updating section configured to update the encoding code table and an encoding flow controlling section configured to control input to the first code table updating section by using a first data amount indicating a data amount of the input symbol. The first data amount is calculated based on the input symbol. The decoder includes a second code table updating section configured to update the decoding code table and a decoding flow controlling section configured to control input to the second code table updating section by using a second data amount indicating a data amount of the output symbol. The second data amount is calculated based on the output symbol in the same way as the calculation of the first data amount.Type: ApplicationFiled: March 4, 2021Publication date: March 17, 2022Applicant: Kioxia CorporationInventors: Masato SUMIYOSHI, Keiri NAKANISHI, Sho KODAMA, Kohei OIKAWA
-
Patent number: 11218163Abstract: A memory system includes a nonvolatile memory, an interface circuit, and a controller configured to upon receipt of a plurality of write commands for storing write data in the nonvolatile memory via the interface circuit, acquire compression-ratio information about the write data associated with each write command, determine a compression ratio of each write data based on the acquired compression-ratio information, and determine an execution order of the write commands based on the determined compression ratio.Type: GrantFiled: September 30, 2020Date of Patent: January 4, 2022Assignee: TOSHIBA MEMORY CORPORATIONInventors: Keiri Nakanishi, Youhei Fukazawa