Patents by Inventor Keishi Okamoto
Keishi Okamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11456269Abstract: A method of fabricating a connection structure is disclosed. The method includes providing a substrate that has a top surface and includes a set of pads for soldering, each of which has a pad surface exposed from the top surface of the substrate. The method also includes applying a surface treatment to a part of the top surface of the substrate close to the pads and the pad surface of each pad so as to make at least the part of the top surface and the pad surfaces of the pads rougher. The surface treatment includes sandblasting.Type: GrantFiled: March 24, 2021Date of Patent: September 27, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Risa Miyazawa, Takahito Watanabe, Hiroyuki Mori, Keishi Okamoto
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Patent number: 11264314Abstract: An interconnection structure is disclosed. The interconnection structure includes a base substrate, a set of conductive pads disposed on the base substrate and an interconnection layer disposed on the base substrate. The interconnection layer has an edge located next to the set of the conductive pads and includes a set of side connection pads located and disposed at the edge of the interconnection layer. Each side connection pad is arranged with respect to a corresponding one of the conductive pads disposed on the base substrate.Type: GrantFiled: September 27, 2019Date of Patent: March 1, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Risa Miyazawa, Takahito Watanabe, Hiroyuki Mori, Keishi Okamoto
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Publication number: 20210343545Abstract: An interconnection layer carrying structure for transferring an interconnection layer onto a substrate is disclosed. The interconnection layer carrying structure includes a support substrate, a release layer on the support substrate; and an interconnection layer on the release layer. The interconnection layer includes an organic insulating material and a set of pads embedded in the organic insulating material. The set of the pads is configured to face towards the support substrate. The support substrate has a base part where the interconnection layer is formed and an extended part extending outside the base part.Type: ApplicationFiled: July 15, 2021Publication date: November 4, 2021Inventors: Keishi Okamoto, Akihiro Horibe, Hiroyuki Mori
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Patent number: 11114308Abstract: An interconnection layer carrying structure for transferring an interconnection layer onto a substrate is disclosed. The interconnection layer carrying structure includes a support substrate, a release layer on the support substrate; and an interconnection layer on the release layer. The interconnection layer includes an organic insulating material and a set of pads embedded in the organic insulating material. The set of the pads is configured to face towards the support substrate. The support substrate has a base part where the interconnection layer is formed and an extended part extending outside the base part.Type: GrantFiled: September 25, 2018Date of Patent: September 7, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Keishi Okamoto, Akihiro Horibe, Hiroyuki Mori
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Publication number: 20210210454Abstract: A method of fabricating a connection structure is disclosed. The method includes providing a substrate that has a top surface and includes a set of pads for soldering, each of which has a pad surface exposed from the top surface of the substrate. The method also includes applying a surface treatment to a part of the top surface of the substrate close to the pads and the pad surface of each pad so as to make at least the part of the top surface and the pad surfaces of the pads rougher. The surface treatment includes sandblasting.Type: ApplicationFiled: March 24, 2021Publication date: July 8, 2021Inventors: Risa Miyazawa, Takahito Watanabe, Hiroyuki Mori, Keishi Okamoto
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Patent number: 11004819Abstract: A method of fabricating a connection structure is disclosed. The method includes providing a substrate that has a top surface and includes a set of pads for soldering, each of which has a pad surface exposed from the top surface of the substrate. The method also includes applying a surface treatment to a part of the top surface of the substrate close to the pads and the pad surface of each pad so as to make at least the part of the top surface and the pad surfaces of the pads rougher.Type: GrantFiled: September 27, 2019Date of Patent: May 11, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Risa Miyazawa, Takahito Watanabe, Hiroyuki Mori, Keishi Okamoto
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Publication number: 20210098404Abstract: A method of fabricating a connection structure is disclosed. The method includes providing a substrate that has a top surface and includes a set of pads for soldering, each of which has a pad surface exposed from the top surface of the substrate. The method also includes applying a surface treatment to a part of the top surface of the substrate close to the pads and the pad surface of each pad so as to make at least the part of the top surface and the pad surfaces of the pads rougher.Type: ApplicationFiled: September 27, 2019Publication date: April 1, 2021Inventors: Risa Miyazawa, Takahito Watanabe, Hiroyuki Mori, Keishi Okamoto
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Publication number: 20210098349Abstract: An interconnection structure is disclosed. The interconnection structure includes a base substrate, a set of conductive pads disposed on the base substrate and an interconnection layer disposed on the base substrate. The interconnection layer has an edge located next to the set of the conductive pads and includes a set of side connection pads located and disposed at the edge of the interconnection layer. Each side connection pad is arranged with respect to a corresponding one of the conductive pads disposed on the base substrate.Type: ApplicationFiled: September 27, 2019Publication date: April 1, 2021Inventors: Risa Miyazawa, Takahito Watanabe, Hiroyuki Mori, Keishi Okamoto
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Patent number: 10643910Abstract: A sacrificial interposer test structure including a release layer, a dummy layer on the release layer, one or more conductive pads embedded in the dummy layer, wherein each of the one or more conductive pads has an exposed surface, and a tie layer on the dummy layer and on each exposed surface of the one or more conductive pads.Type: GrantFiled: August 17, 2018Date of Patent: May 5, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hiroyuki Mori, Keishi Okamoto
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Patent number: 10622311Abstract: A technique for interconnecting chips by using an interconnection substrate is disclosed. The interconnection substrate includes a base substrate, a first group of electrodes on the base substrate for a first chip to be mounted, and a second group of electrodes on the base substrate for a second chip to be mounted. The interconnection substrate further includes an interconnection layer that includes a first set of pads for the first chip, a second set of pads for the second chip, traces and an organic insulating material. The interconnection layer is disposed on the base substrate and located within a defined area on the base substrate between the first group of electrodes and the second group of the electrodes.Type: GrantFiled: August 10, 2017Date of Patent: April 14, 2020Assignee: International Business Machines CorporationInventors: Akihiro Horibe, Hiroyuki Mori, Keishi Okamoto
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Publication number: 20200098592Abstract: An interconnection layer carrying structure for transferring an interconnection layer onto a substrate is disclosed. The interconnection layer carrying structure includes a support substrate, a release layer on the support substrate; and an interconnection layer on the release layer. The interconnection layer includes an organic insulating material and a set of pads embedded in the organic insulating material. The set of the pads is configured to face towards the support substrate. The support substrate has a base part where the interconnection layer is formed and an extended part extending outside the base part.Type: ApplicationFiled: September 25, 2018Publication date: March 26, 2020Inventors: Keishi Okamoto, Akihiro Horibe, Hiroyuki Mori
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Patent number: 10595399Abstract: An organic substrate includes a core layer including organic materials; a first buildup layer on a top surface of the core layer; a second buildup layer on a bottom surface of the core layer; and at least one correction layer formed on at least one part of surfaces of the first buildup layer and the second buildup layer, wherein the correction layer has a thickness which has been calculated using properties of constituent materials including the coefficient of thermal expansion (CTE) and the Young's modulus of the core layer, and CTEs and the Young's modulus of the first and the second buildup layers for reducing warpage of the organic substrate.Type: GrantFiled: January 16, 2018Date of Patent: March 17, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sayuri Hada, Hiroyuki Mori, Keishi Okamoto
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Patent number: 10529665Abstract: A technique for interconnecting chips by using an interconnection substrate is disclosed. The interconnection substrate includes a base substrate, a first group of electrodes on the base substrate for a first chip to be mounted, and a second group of electrodes on the base substrate for a second chip to be mounted. The interconnection substrate further includes an interconnection layer that includes a first set of pads for the first chip, a second set of pads for the second chip, traces and an organic insulating material. The interconnection layer is disposed on the base substrate and located within a defined area on the base substrate between the first group of electrodes and the second group of the electrodes.Type: GrantFiled: November 6, 2017Date of Patent: January 7, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Akihiro Horibe, Hiroyuki Mori, Keishi Okamoto
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Publication number: 20190051605Abstract: A technique for interconnecting chips by using an interconnection substrate is disclosed. The interconnection substrate includes a base substrate, a first group of electrodes on the base substrate for a first chip to be mounted, and a second group of electrodes on the base substrate for a second chip to be mounted. The interconnection substrate further includes an interconnection layer that includes a first set of pads for the first chip, a second set of pads for the second chip, traces and an organic insulating material. The interconnection layer is disposed on the base substrate and located within a defined area on the base substrate between the first group of electrodes and the second group of the electrodes.Type: ApplicationFiled: November 6, 2017Publication date: February 14, 2019Inventors: Akihiro Horibe, Hiroyuki Mori, Keishi Okamoto
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Publication number: 20190053370Abstract: An organic substrate includes a core layer including organic materials; a first buildup layer on a top surface of the core layer; a second buildup layer on a bottom surface of the core layer; and at least one correction layer formed on at least one part of surfaces of the first buildup layer and the second buildup layer, wherein the correction layer has a thickness which has been calculated using properties of constituent materials including the coefficient of thermal expansion (CTE) and the Young's modulus of the core layer, and CTEs and the Young's modulus of the first and the second buildup layers for reducing warpage of the organic substrate.Type: ApplicationFiled: January 16, 2018Publication date: February 14, 2019Inventors: Sayuri Hada, Hiroyuki Mori, Keishi Okamoto
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Publication number: 20190051603Abstract: A technique for interconnecting chips by using an interconnection substrate is disclosed. The interconnection substrate includes a base substrate, a first group of electrodes on the base substrate for a first chip to be mounted, and a second group of electrodes on the base substrate for a second chip to be mounted. The interconnection substrate further includes an interconnection layer that includes a first set of pads for the first chip, a second set of pads for the second chip, traces and an organic insulating material. The interconnection layer is disposed on the base substrate and located within a defined area on the base substrate between the first group of electrodes and the second group of the electrodes.Type: ApplicationFiled: August 10, 2017Publication date: February 14, 2019Inventors: Akihiro Horibe, Hiroyuki Mori, Keishi Okamoto
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Publication number: 20190006250Abstract: A sacrificial interposer test structure including a release layer, a dummy layer on the release layer, one or more conductive pads embedded in the dummy layer, wherein each of the one or more conductive pads has an exposed surface, and a tie layer on the dummy layer and on each exposed surface of the one or more conductive pads.Type: ApplicationFiled: August 17, 2018Publication date: January 3, 2019Inventors: Hiroyuki Mori, Keishi Okamoto
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Patent number: 10141278Abstract: Highly reliable chip mounting is accomplished by using a substrate having such a shape that a stress exerted on a flip-chip-connected chip can be reduced, so that the stress exerted on the chip is reduced and separation of an interlayer insulating layer having a low dielectric constant (low-k) is minimized. Specifically, in a chip mounting structure, a chip including an interlayer insulating layer having a low dielectric constant (low-k) is flip-chip connected to a substrate via bumps is shown. In the chip mounting structure, the substrate has such a shape that a mechanical stress exerted on the interlayer insulating layer at corner portions of the chip due to a thermal stress is reduced, the thermal stress occurring due to a difference in coefficient of thermal expansion between the chip and the substrate.Type: GrantFiled: November 6, 2017Date of Patent: November 27, 2018Assignee: International Business Machines CorporationInventors: Akihiro Horibe, Keiji Matsumoto, Keishi Okamoto, Kazushige Toriyama
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Patent number: 10109540Abstract: A sacrificial interposer test structure including a release layer, a dummy layer on the release layer, one or more conductive pads embedded in the dummy layer, wherein each of the one or more conductive pads has an exposed surface, and a tie layer on the dummy layer and on each exposed surface of the one or more conductive pads.Type: GrantFiled: June 8, 2016Date of Patent: October 23, 2018Assignee: International Business Machines CorporationInventors: Hiroyuki Mori, Keishi Okamoto
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Patent number: 10090586Abstract: A joined structure which is configured such that a space between adjacent substrates is filled with a filling material. The joined structure includes a first substrate having a first conductor formed on a surface of the first substrate, a second substrate having a second conductor formed on a surface of the second substrate, arranged so that a surface of the first substrate faces a surface of the second substrate, a connecting conductor which electrically connects the first conductor and the second conductor, and a filling material between the first substrate and the second substrate. The filling material is formed into such a shape that a space is provided which corresponds to at least one of the first conductor, the second and the connecting conductor.Type: GrantFiled: July 10, 2017Date of Patent: October 2, 2018Assignee: International Business Machines CorporationInventors: Toyohiro Aoki, Noam Kaminski, Keishi Okamoto, Kazushige Toriyama