Patents by Inventor Keishi Sakanushi
Keishi Sakanushi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9190150Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a memory cell array including a plurality of stacked memory cells, a plurality of first wirings electrically connected to the plurality of memory cells, a plurality of first contacts electrically connected to part of the plurality of first wirings and arranged in a first direction parallel to the semiconductor substrate, a plurality of second contacts electrically connected to part of the plurality of first wirings and arranged in the first direction alternately with the first contacts, a plurality of third contacts electrically connected to the first contacts and displaced from the first contacts in the first direction, and a plurality of fourth contacts electrically connected to the second contacts and displaced from the second contacts in a second direction perpendicular to the first direction.Type: GrantFiled: September 4, 2013Date of Patent: November 17, 2015Assignee: Kabushiki Kaisha ToshibaInventor: Keishi Sakanushi
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Patent number: 9166624Abstract: An error-correcting code processing method includes: calculating descending symbols or ascending symbols or both, and calculating, as a parity, exclusive OR of all elements of an information symbol sequence; one or both of calculating exclusive OR for each element of the descending symbols, to generate low-order n bits of the descending symbols and calculating exclusive OR for each element of the ascending symbols, to generate low-order n bits of the ascending symbols; one or both of calculating exclusive OR of elements obtained by selecting, in descending order, elements from an element sequence resulting from arranging parities, to generate a high-order m bit of the descending symbols and calculating exclusive OR of elements obtained by selecting, in ascending order, elements from the element sequence, to generate a high-order m bit of the ascending symbols; and outputting the descending symbols or the ascending symbols or both as check symbols or a syndrome.Type: GrantFiled: May 11, 2011Date of Patent: October 20, 2015Assignee: OSAKA UNIVERSITYInventors: Masaharu Imai, Yoshinori Takeuchi, Keishi Sakanushi, Takashi Hamabe, Kazuki Ohya, Masaaki Abe
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Patent number: 9158878Abstract: According to one embodiment, a method is disclosed for designing an integrated circuit by a computer including an input unit, a memory unit, a calculating unit, and an output unit. The method can include storing a design model in the memory unit. The design model has parameters of physical quantities of active elements, passive elements, and an interconnection pattern included in the integrated circuit. The design model has an algorithm generating a circuit layout from values of the parameters. The method can include inputting the values of the parameters based on a first design specification of the integrated circuit by the input unit, generating a first circuit layout of the active elements, the passive elements, and the interconnection pattern by the calculating unit using the design model from the values of the parameters received by the input unit, and outputting the first circuit layout by the output unit.Type: GrantFiled: January 23, 2014Date of Patent: October 13, 2015Assignee: Kabushiki Kaisha ToshibaInventor: Keishi Sakanushi
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Publication number: 20150260768Abstract: A detection method of an algorithm in an integrated circuit according to an embodiment includes: acquiring time waveforms of physical information from the integrated circuit in respective operations, by causing the integrated circuit to operate with different input values a plurality of times; calculating intermediate values corresponding to the input values or output values of the integrated circuit, based on a known algorithm; grouping the time waveforms of the physical information based on the intermediate values; and evaluating whether or not the time waveforms of the physical information depend on the intermediate value, and if the time waveforms depend on the intermediate value, determining that the integrated circuit executes the algorithm.Type: ApplicationFiled: August 6, 2014Publication date: September 17, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Keishi SAKANUSHI, Katsuhiko IWAI
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Publication number: 20150074618Abstract: In a design layout correcting method of an embodiment, a design layout of a circuit pattern is divided to a first mask pattern and a second mask pattern. The mask pattern of the pattern defect area of the first or second mask pattern is set as the correcting target pattern. A correcting target region and a verifying region are set within the first or second mask pattern. The correcting target pattern is corrected within the correcting target region, and the first and second mask patterns are verified within the verifying region.Type: ApplicationFiled: February 27, 2014Publication date: March 12, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Yoko Yokoyama, Keishi Sakanushi, Chikaaki Kodama
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Patent number: 8972907Abstract: In a design layout correcting method of an embodiment, a design layout of a circuit pattern is divided to a first mask pattern and a second mask pattern. The mask pattern of the pattern defect area of the first or second mask pattern is set as the correcting target pattern. A correcting target region and a verifying region are set within the first or second mask pattern. The correcting target pattern is corrected within the correcting target region, and the first and second mask patterns are verified within the verifying region.Type: GrantFiled: February 27, 2014Date of Patent: March 3, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Yoko Yokoyama, Keishi Sakanushi, Chikaaki Kodama
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Publication number: 20150058816Abstract: According to one embodiment, a method is disclosed for designing an integrated circuit by a computer including an input unit, a memory unit, a calculating unit, and an output unit. The method can include storing a design model in the memory unit. The design model has parameters of physical quantities of active elements, passive elements, and an interconnection pattern included in the integrated circuit. The design model has an algorithm generating a circuit layout from values of the parameters. The method can include inputting the values of the parameters based on a first design specification of the integrated circuit by the input unit, generating a first circuit layout of the active elements, the passive elements, and the interconnection pattern by the calculating unit using the design model from the values of the parameters received by the input unit, and outputting the first circuit layout by the output unit.Type: ApplicationFiled: January 23, 2014Publication date: February 26, 2015Applicant: Kabushiki Kaisha ToshibaInventor: Keishi SAKANUSHI
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Publication number: 20140293700Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a memory cell array including a plurality of stacked memory cells, a plurality of first wirings electrically connected to the plurality of memory cells, a plurality of first contacts electrically connected to part of the plurality of first wirings and arranged in a first direction parallel to the semiconductor substrate, a plurality of second contacts electrically connected to part of the plurality of first wirings and arranged in the first direction alternately with the first contacts, a plurality of third contacts electrically connected to the first contacts and displaced from the first contacts in the first direction, and a plurality of fourth contacts electrically connected to the second contacts and displaced from the second contacts in a second direction perpendicular to the first direction.Type: ApplicationFiled: September 4, 2013Publication date: October 2, 2014Applicant: Kabushiki Kaisha ToshibaInventor: Keishi SAKANUSHI
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Publication number: 20130061115Abstract: An error-correcting code processing method includes: calculating descending symbols or ascending symbols or both, and calculating, as a parity, exclusive OR of all elements of an information symbol sequence; one or both of calculating exclusive OR for each element of the descending symbols, to generate low-order n bits of the descending symbols and calculating exclusive OR for each element of the ascending symbols, to generate low-order n bits of the ascending symbols; one or both of calculating exclusive OR of elements obtained by selecting, in descending order, elements from an element sequence resulting from arranging parities, to generate a high-order m bit of the descending symbols and calculating exclusive OR of elements obtained by selecting, in ascending order, elements from the element sequence, to generate a high-order m bit of the ascending symbols; and outputting the descending symbols or the ascending symbols or both as check symbols or a syndrome.Type: ApplicationFiled: May 11, 2011Publication date: March 7, 2013Inventors: Masaharu Imai, Yoshinori Takeuchi, Keishi Sakanushi, Takashi Hamabe, Kazuki Ohya, Masaaki Abe