Patents by Inventor Keishi Tachikawa

Keishi Tachikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9136409
    Abstract: An optical device includes a first region and an isolating layer which are each provided in a semiconductor substrate. The first region configures a photoelectric converter and includes at least an impurity of a first conductivity type. The isolating layer is configured to inhibit passage of electrons. The isolating layer includes a second region which is below the first region and which includes an impurity of a second conductivity type, a third region which surrounds the first region in plan-view thereof and which includes an impurity of the second conductivity type, and a fourth region which surrounds the second region in plan-view thereof and which is connected to the third region. The fourth region is greater in width than a connecting part of the third region which connects the third region to the fourth region.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: September 15, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Keishi Tachikawa
  • Publication number: 20140061844
    Abstract: An optical device includes a first region and an isolating layer which are each provided in a semiconductor substrate. The first region configures a photoelectric converter and includes at least an impurity of a first conductivity type. The isolating layer is configured to inhibit passage of electrons. The isolating layer includes a second region which is below the first region and which includes an impurity of a second conductivity type, a third region which surrounds the first region in plan-view thereof and which includes an impurity of the second conductivity type, and a fourth region which surrounds the second region in plan-view thereof and which is connected to the third region. The fourth region is greater in width than a connecting part of the third region which connects the third region to the fourth region.
    Type: Application
    Filed: November 6, 2013
    Publication date: March 6, 2014
    Applicant: PANASONIC CORPORATION
    Inventor: Keishi TACHIKAWA
  • Publication number: 20100308384
    Abstract: A photodiode has a carrier accumulation layer of a second conductivity type and a surface area of a first conductivity type deposited in order from an inside towards a surface of a first conductivity type well region. A transfer transistor is formed so that a transfer gate electrode of the transfer transistor partially overlaps the surface layer of the photodiode and is formed above a surface of the first conductivity type well region with a gate insulating film therebetween. The surface layer includes a first surface layer, which partially overlaps the transfer gate electrode in the direction of the x-axis, and a second surface layer adjacent to the first surface layer. A concentration of the impurity of the first conductivity type is higher in the second surface layer than in the first surface layer.
    Type: Application
    Filed: April 27, 2010
    Publication date: December 9, 2010
    Inventors: Morikazu TSUNO, Keishi TACHIKAWA
  • Patent number: 7732843
    Abstract: Forming an impurity region 6 and an impurity region 5 having a lower concentration than the impurity region 6 in a lower layer region of a gate electrode close to the boundary with a signal electron-voltage conversion section of a horizontal CCD outlet makes it possible to smooth a potential distribution at the time of transfer, improve the transfer efficiency, increase the number of saturated electrons and reduce variations in the transfer efficiency and variations in saturation.
    Type: Grant
    Filed: August 4, 2008
    Date of Patent: June 8, 2010
    Assignee: Panasonic Corporation
    Inventor: Keishi Tachikawa
  • Publication number: 20090039395
    Abstract: Forming an impurity region 6 and an impurity region 5 having a lower concentration than the impurity region 6 in a lower layer region of a gate electrode close to the boundary with a signal electron-voltage conversion section of a horizontal CCD outlet makes it possible to smooth a potential distribution at the time of transfer, improve the transfer efficiency, increase the number of saturated electrons and reduce variations in the transfer efficiency and variations in saturation.
    Type: Application
    Filed: August 4, 2008
    Publication date: February 12, 2009
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventor: Keishi Tachikawa
  • Publication number: 20070210346
    Abstract: A gate electrode region of a junction transistor in a signal charge-voltage converter is allowed to have a structure that a gentle potential gradient is formed without generation of a potential barrier. Thus, it is possible to readily realize a signal charge-voltage converter which is high in S/N ratio without generation of reset noise and is excellent in signal charge-voltage conversion efficiency.
    Type: Application
    Filed: March 6, 2007
    Publication date: September 13, 2007
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventor: Keishi Tachikawa
  • Patent number: 7259394
    Abstract: A vertical transfer charge-coupled device for vertically transferring signal charges, a horizontal transfer charge-coupled device for receiving and horizontally transferring the transferred signal charges, an unwanted electron eliminator, and a potential barrier between the horizontal transfer charge-coupled device and the unwanted electron eliminator are provided on a semiconductor substrate. The potential barrier includes a first n-type diffusion layer, a second n-type diffusion layer that is in contact with one end thereof, and a third n-type diffusion layer that is in contact with the other end. The second n-type diffusion layer and the third n-type diffusion layer have higher impurity concentrations than the first n-type diffusion layer.
    Type: Grant
    Filed: May 5, 2005
    Date of Patent: August 21, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Keishi Tachikawa
  • Publication number: 20050247935
    Abstract: A vertical transfer charge-coupled device for vertically transferring signal charges, a horizontal transfer charge-coupled device for receiving and horizontally transferring the transferred signal charges, an unwanted electron eliminator, and a potential barrier between the horizontal transfer charge-coupled device and the unwanted electron eliminator are provided on a semiconductor substrate. The potential barrier includes a first n-type diffusion layer, a second n-type diffusion layer that is in contact with one end thereof, and a third n-type diffusion layer that is in contact with the other end. The second n-type diffusion layer and the third n-type diffusion layer have higher impurity concentrations than the first n-type diffusion layer.
    Type: Application
    Filed: May 5, 2005
    Publication date: November 10, 2005
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventor: Keishi Tachikawa
  • Patent number: 6046069
    Abstract: A solid-state image pick-up device having a structure in which the amount of transferred charges is not reduced in a vertical CCD portion even if a pixel portion is made finer, and a method for manufacturing the solid-state image pick-up device are provided. A first p-type well and a second p-type well are formed on an N (100) silicon substrate. A vertical CCD n.sup.+ layer is formed in the second p-type well 3. Then, impurity ions are implanted into a surface layer of the N (100) silicon substrate including an upper layer portion of the vertical CCD n.sup.+ layer to form a p.sup.- layer. An isolating portion for isolating photodiode portions from the vertical CCD n.sup.+ layer and a read control portion for controlling the read of charges from the photodiode n layer are simultaneously formed on a portion adjacent to the vertical CCD n.sup.+ layer.
    Type: Grant
    Filed: February 5, 1997
    Date of Patent: April 4, 2000
    Assignee: Matsushita Electronics Corporation
    Inventors: Katsuya Ishikawa, Takao Kuroda, Yuji Matsuda, Masahiko Niwayama, Keishi Tachikawa
  • Patent number: 5786607
    Abstract: A solid-state image pick-up device having a structure in which the amount of transferred charges is not reduced in a vertical CCD portion even if a pixel portion is made finer, and a method for manufacturing the solid-state image pick-up device are provided. A first p-type well and a second p-type well are formed on an N (100) silicon substrate. A vertical CCD n.sup.+ layer is formed in the second p-type well 3. Then, impurity ions are implanted into a surface layer of the N (100) silicon substrate including an upper layer portion of the vertical CCD n.sup.+ layer to form a p.sup.- layer. An isolating portion for isolating photodiode portions from the vertical CCD n.sup.+ layer and a read control portion for controlling the read of charges from the photodiode n layer are simultaneously formed on a portion adjacent to the vertical CCD n.sup.+ layer.
    Type: Grant
    Filed: May 29, 1996
    Date of Patent: July 28, 1998
    Assignee: Matsushita Electronics Corporation
    Inventors: Katsuya Ishikawa, Takao Kuroda, Yuji Matsuda, Masahiko Niwayama, Keishi Tachikawa