Abstract: A membrane defect inspection method is for a membrane module set including a plurality of membrane modules connected in parallel under a straight pipe portion of gas detection piping extending in a horizontal direction and communicating with primary spaces in the plurality of membrane modules to which raw water is supplied or secondary spaces. The method includes a gas injection process where gas is injected into spaces opposite to the primary spaces or the secondary spaces communicating with the gas detection piping while the gas detection piping is filled with water, and an echo detection process where an ultrasonic sensor is brought into contact with an end portion of the straight pipe portion of the gas detection piping, and a reflected wave of an ultrasonic wave transmitted from the ultrasonic sensor is detected.

Abstract: A membrane filtration device includes a plurality of membrane separation units vertically disposed in multiple stages. The membrane separation unit has a primary side communicating with a backwash drainage system and a flushing-air supply system to receive supplied raw water and a secondary side communicating with a backwash-water supply system to collect permeate. The backwash-water supply system includes a backwash-water main pipe and a plurality of backwash-water branch pipes to feed the backwash water into the membrane separation units. The backwash drainage system includes a plurality of backwash-drainage branch pipes and a backwash-drainage main pipe connected in parallel to the backwash-drainage branch pipes. The flushing-air supply system includes an air main pipe for passing flushing air upward and a plurality of air branch pipes for feeding flushing air into the membrane separation units, the air branch pipes being connected in parallel to the air main pipe.

Abstract: The present invention provides a diode chip, including: a semiconductor chip, including a p-type first semiconductor layer and an n-type second semiconductor layer formed on the first semiconductor layer; a first pad separation trench, formed on the semiconductor chip in a manner of penetrating the second semiconductor layer till reaching the first semiconductor layer, and forming a first internal parasitic capacitance between the first semiconductor layer and the second semiconductor layer by separating a portion of the semiconductor chip from other regions; an inter-insulation layer, covering the second semiconductor layer; and a first electrode layer, being opposite to the region separated by the first pad separation trench with the inter-insulation layer interposed in between, and forming, between the first electrode layer and the semiconductor chip, a first external parasitic capacitance connected in series to the first internal parasitic capacitance.

Abstract: A membrane defect inspection method that can detect damage in a filtrate membrane and can detect presence or absence of damage or a seal defect in a membrane module; and the method is for a membrane module set including multiple membrane modules connected under gas detection piping communicating with primary spaces of the multiple membrane modules where raw water is supplied or secondary spaces in multiple membrane modules where treated water is extracted after the raw water is filtrated by membranes. The method includes a gas injection process where gas is injected into spaces opposite the primary or secondary spaces communicating with gas detection piping in the multiple membrane modules while the gas detection piping is filled with water, and a vibration detection process where a vibration sensor is brought into contact with a protrusion protruding outward from the gas detection piping to detect vibration of the gas detection piping.

Abstract: A membrane defect inspection method is for a membrane module set including a plurality of membrane modules connected in parallel under a straight pipe portion of gas detection piping extending in a horizontal direction and communicating with primary spaces in the plurality of membrane modules to which raw water is supplied or secondary spaces. The method includes a gas injection process where gas is injected into spaces opposite to the primary spaces or the secondary spaces communicating with the gas detection piping while the gas detection piping is filled with water, and an echo detection process where an ultrasonic sensor is brought into contact with an end portion of the straight pipe portion of the gas detection piping, and a reflected wave of an ultrasonic wave transmitted from the ultrasonic sensor is detected.

Abstract: The present disclosure provides a chip capacitor, including: a first capacitor unit formed over a substrate and including a first lower electrode, first dielectric layer and first upper electrode; a second insulating layer over the first capacitor unit; a second conductive layer over the second insulating layer, and includes a first wiring portion and a second wiring portion, the first wiring portion being connected to the first lower electrode by a first contact via and connected to a first pad by a third contact via, the second wiring portion being connected to the first upper electrode by a second contact via and connected to a second pad by a fourth contact via; a first external electrode connected to the first wiring portion; and a second external electrode connected to the second wiring portion.

Abstract: The present invention provides a diode chip, including: a semiconductor chip, including a p-type first semiconductor layer and an n-type second semiconductor layer formed on the first semiconductor layer; a first pad separation trench, formed on the semiconductor chip in a manner of penetrating the second semiconductor layer till reaching the first semiconductor layer, and forming a first internal parasitic capacitance between the first semiconductor layer and the second semiconductor layer by separating a portion of the semiconductor chip from other regions; an inter-insulation layer, covering the second semiconductor layer; and a first electrode layer, being opposite to the region separated by the first pad separation trench with the inter-insulation layer interposed in between, and forming, between the first electrode layer and the semiconductor chip, a first external parasitic capacitance connected in series to the first internal parasitic capacitance.

Abstract: The present disclosure provides a diode chip capable of attaining excellent electrical characteristics. The present disclosure provides a diode chip (1), including: a semiconductor chip (10) having a first main surface (11); a first pin junction portion (31) formed on a surface of the first main surface (11) with a first polarity direction; a first diode pair (37) (rectifier pair) including a first pn junction portion (35) separated from the first pin junction portion (31) and formed in the semiconductor chip (10) with the first polarity direction and a first reversed pin junction portion (38) connected to the first pn junction portion (35) in reversed direction and formed on the first main surface (11) with a second polarity direction; and a first junction separation trench (46) formed on the first main surface (11) in a manner of separating the first pin junction portion (31) and the first diode pair (37).

Abstract: A chip part is provided that includes a substrate in which an element region and an electrode region are set, an insulating film (a first insulating film and a second insulating film) which is formed on the substrate and which selectively includes an internal concave/convex structure in the electrode region on a surface, a first connection electrode and a second connection electrode which include, at a bottom portion, an anchor portion entering the concave portion of the internal concave/convex structure and which include an external concave/convex structure on a surface on the opposite side and a circuit element which is disposed in the element region and which is electrically connected to the first connection electrode and the second connection electrode.

Abstract: The composite chip component includes: plurality of chip elements which are disposed so as to be mutually spaced apart upon a common substrate, and which have mutually different functions; and a pair of electrodes which, in each of the chip elements, are formed on the surface of the substrate. As a result, it is possible to reduce the bond area (footprint) for the mounting substrate, and therefore, it is possible to provide a composite chip component capable of achieving efficiency of mounting operation.

Abstract: The present disclosure provides a chip capacitor, including: a first capacitor unit formed over a substrate and including a first lower electrode, first dielectric layer and first upper electrode; a second insulating layer over the first capacitor unit; a second conductive layer over the second insulating layer, and includes a first wiring portion and a second wiring portion, the first wiring portion being connected to the first lower electrode by a first contact via and connected to a first pad by a third contact via, the second wiring portion being connected to the first upper electrode by a second contact via and connected to a second pad by a fourth contact via; a first external electrode connected to the first wiring portion; and a second external electrode connected to the second wiring portion.

Abstract: A chip capacitor includes a substrate having a main surface, a first conductive film including a first connecting region and a first capacitor forming region and formed on the main surface of the substrate, a dielectric film covering the first capacitor forming region of the first conductive film, a second conductive film including a second connecting region facing to the first capacitor forming region of the first conductive film across the dielectric film, and a second capacitor forming region facing to the first capacitor forming region of the first conductive film across the dielectric film, a first external electrode electrically connected to the first connecting region of the first conductive film, and a second external electrode electrically connected to the second connecting region of the second conductive film.

Abstract: A chip capacitor according to the present invention includes a substrate, a pair of external electrodes formed on the substrate, a capacitor element connected between the pair of external electrodes, and a bidirectional diode connected between the pair of external electrodes and in parallel to the capacitor element. Also, a circuit assembly according to the present invention includes the chip capacitor according to the present invention and a mounting substrate having lands, soldered to the external electrodes, on a mounting surface facing a front surface of the substrate.

Abstract: A membrane casing that watertightly houses a membrane element for filtering raw water includes a tubular casing main body, a lid body, and a pressing mechanism. The casing main body houses a membrane element. The lid body fits an opening end of the casing main body and is movable in the axial direction of the casing main body while maintaining the attitude and while securing watertightness with the casing main body. The pressing mechanism and presses the lid body to press and hold the membrane element housed in the casing main body. The membrane casing has a simple configuration capable of watertightly securing using a predetermined pressing force by accommodating variations in size of the membrane element, even if the membrane casing cannot be formed into a cylindrical shape.

Abstract: The composite chip component includes: plurality of chip elements which are disposed so as to be mutually spaced apart upon a common substrate, and which have mutually different functions; and a pair of electrodes which, in each of the chip elements, are formed on the surface of the substrate. As a result, it is possible to reduce the bond area (footprint) for the mounting substrate, and therefore, it is possible to provide a composite chip component capable of achieving efficiency of mounting operation.

Abstract: The composite chip component includes: plurality of chip elements which are disposed so as to be mutually spaced apart upon a common substrate, and which have mutually different functions; and a pair of electrodes which, in each of the chip elements, are formed on the surface of the substrate. As a result, it is possible to reduce the bond area (footprint) for the mounting substrate, and therefore, it is possible to provide a composite chip component capable of achieving efficiency of mounting operation.

Abstract: A chip capacitor according to the present invention includes a substrate, a pair of external electrodes formed on the substrate, a capacitor element connected between the pair of external electrodes, and a bidirectional diode connected between the pair of external electrodes and in parallel to the capacitor element. Also, a circuit assembly according to the present invention includes the chip capacitor according to the present invention and a mounting substrate having lands, soldered to the external electrodes, on a mounting surface facing a front surface of the substrate.

Abstract: A chip capacitor according to the present invention includes a substrate, a pair of external electrodes formed on the substrate, a capacitor element connected between the pair of external electrodes, and a bidirectional diode connected between the pair of external electrodes and in parallel to the capacitor element. Also, a circuit assembly according to the present invention includes the chip capacitor according to the present invention and a mounting substrate having lands, soldered to the external electrodes, on a mounting surface facing a front surface of the substrate.

Abstract: A chip part is provided that includes a substrate in which an element region and an electrode region are set, an insulating film (a first insulating film and a second insulating film) which is formed on the substrate and which selectively includes an internal concave/convex structure in the electrode region on a surface, a first connection electrode and a second connection electrode which include, at a bottom portion, an anchor portion entering the concave portion of the internal concave/convex structure and which include an external concave/convex structure on a surface on the opposite side and a circuit element which is disposed in the element region and which is electrically connected to the first connection electrode and the second connection electrode.

Abstract: A chip capacitor includes a substrate having a main surface, a first conductive film including a first connecting region and a first capacitor forming region and formed on the main surface of the substrate, a dielectric film covering the first capacitor forming region of the first conductive film, a second conductive film including a second connecting region facing to the first capacitor forming region of the first conductive film across the dielectric film, and a second capacitor forming region facing to the first capacitor forming region of the first conductive film across the dielectric film, a first external electrode electrically connected to the first connecting region of the first conductive film, and a second external electrode electrically connected to the second connecting region of the second conductive film.