Patents by Inventor Keishi WATANABE

Keishi WATANABE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12263778
    Abstract: Provided is a bracket attachment structure for detachably attaching a bracket to which a radar unit is attached to an outer lens. In the bracket attachment structure, the outer lens is attached to a lamp housing and constitutes a lamp chamber in which a lamp unit is disposed between the outer lens and the lamp housing, the outer lens includes a recessed part, the bracket includes a bracket main body disposed in the recessed part and an extension part extending from an other end side on a side opposite to one end side of the bracket main body to the outside of the recessed part and detachably fixed to an attachment partner, a restricting part is provided on a bottom surface of the recessed part, and a fitting recessed part into which the restricting part is inserted and fitted is provided in the bracket main body.
    Type: Grant
    Filed: July 26, 2024
    Date of Patent: April 1, 2025
    Assignees: STANLEY ELECTRIC CO., LTD., HONDA MOTOR CO., LTD.
    Inventors: Yuuri Oyabu, Masaki Ando, Yuki Sasanuma, Takato Watanabe, Keishi Shiomi
  • Patent number: 12246290
    Abstract: A membrane filtration device includes a plurality of membrane separation units vertically disposed in multiple stages. The membrane separation unit has a primary side communicating with a backwash drainage system and a flushing-air supply system to receive supplied raw water and a secondary side communicating with a backwash-water supply system to collect permeate. The backwash-water supply system includes a backwash-water main pipe and a plurality of backwash-water branch pipes to feed the backwash water into the membrane separation units. The backwash drainage system includes a plurality of backwash-drainage branch pipes and a backwash-drainage main pipe connected in parallel to the backwash-drainage branch pipes. The flushing-air supply system includes an air main pipe for passing flushing air upward and a plurality of air branch pipes for feeding flushing air into the membrane separation units, the air branch pipes being connected in parallel to the air main pipe.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: March 11, 2025
    Assignee: KUBOTA CORPORATION
    Inventors: Shintaro Nishimoto, Keishi Watanabe, Tetsuya Uenaka, Fang Zhao, Akira Matsunaga
  • Publication number: 20250033553
    Abstract: A detector-attached vehicular lighting device includes a lighting unit and a detection unit. The lighting unit includes a light source and a lens. The lens is formed with a storage recess that is recessed in a counter-detection direction other than a detection direction. The detection unit includes a detector, a bracket, and a cover. At least a part of the detector is stored in the storage recess. The bracket supports the detector from a side in the counter-detection direction. The cover is provided with a flange that projects in the counter-detection direction. The cover is attached to the bracket by engagement of the bracket and the flange at a predetermined location of engagement. The detector has, at an end in the detection direction, a detection surface for detecting an object. The flange extends, above the detector, further toward the side in the counter-detection direction than the detection surface.
    Type: Application
    Filed: July 23, 2024
    Publication date: January 30, 2025
    Inventors: Yuki SASANUMA, Takato WATANABE, Keishi SHIOMI
  • Publication number: 20250035779
    Abstract: A detector-attached vehicular lighting device includes a lighting unit and a detection unit. The detection unit includes a detector, a bracket, and a cover. At least a part of the detector is stored in a storage recess on a lens of the lighting unit. The bracket supports the detector from a side in a counter-detection direction. A flange of the cover is in engagement with the bracket. A gap is formed between an inner peripheral surface of the storage recess and the cover. A part of the inner peripheral surface of the storage recess, which is facing the gap, is provided with a lens side guide surface extending along an insertion virtual line heading from the gap toward a location of the engagement. A part of the cover, which is facing the gap, is provided with a cover side guide surface extending along the insertion virtual line.
    Type: Application
    Filed: July 23, 2024
    Publication date: January 30, 2025
    Inventors: Yuki SASANUMA, Takato WATANABE, Keishi SHIOMI
  • Publication number: 20250033555
    Abstract: Provided is a bracket attachment structure for detachably attaching a bracket to which a radar unit is attached to an outer lens. In the bracket attachment structure, the outer lens is attached to a lamp housing and constitutes a lamp chamber in which a lamp unit is disposed between the outer lens and the lamp housing, the outer lens includes a recessed part, the bracket includes a bracket main body disposed in the recessed part and an extension part extending from an other end side on a side opposite to one end side of the bracket main body to the outside of the recessed part and detachably fixed to an attachment partner, a restricting part is provided on a bottom surface of the recessed part, and a fitting recessed part into which the restricting part is inserted and fitted is provided in the bracket main body.
    Type: Application
    Filed: July 26, 2024
    Publication date: January 30, 2025
    Inventors: Yuuri OYABU, Masaki ANDO, Yuki SASANUMA, Takato WATANABE, Keishi SHIOMI
  • Publication number: 20250033554
    Abstract: Provided is a bracket attachment structure for detachably attaching a bracket to which a radar unit is attached to an outer lens. In the bracket attachment structure, the outer lens is attached to a lamp housing and constitutes a lamp chamber in which a lamp unit is disposed between the outer lens and the lamp housing, the outer lens includes a recessed part and an engaged part formed on an inner wall of the recessed part, and the bracket includes a bracket main body disposed in the recessed part, an engaging part provided on the bracket main body and inserted into the engaged part, an extension part extending to an outside of the recessed part and detachably fixed to an attachment partner, and at least one spring part disposed between the rear surface of the bracket main body and a bottom surface of the recessed part.
    Type: Application
    Filed: July 26, 2024
    Publication date: January 30, 2025
    Inventors: Takehiro MATSUMOTO, Yuki SASANUMA, Takato WATANABE, Keishi SHIOMI
  • Patent number: 12113064
    Abstract: The present disclosure provides a diode chip capable of attaining excellent electrical characteristics. The present disclosure provides a diode chip (1), including: a semiconductor chip (10) having a first main surface (11); a first pin junction portion (31) formed on a surface of the first main surface (11) with a first polarity direction; a first diode pair (37) (rectifier pair) including a first pn junction portion (35) separated from the first pin junction portion (31) and formed in the semiconductor chip (10) with the first polarity direction and a first reversed pin junction portion (38) connected to the first pn junction portion (35) in reversed direction and formed on the first main surface (11) with a second polarity direction; and a first junction separation trench (46) formed on the first main surface (11) in a manner of separating the first pin junction portion (31) and the first diode pair (37).
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: October 8, 2024
    Assignee: ROHM CO., LTD.
    Inventors: Keishi Watanabe, Junya Yamagami
  • Patent number: 11986773
    Abstract: A membrane defect inspection method that can detect damage in a filtrate membrane and can detect presence or absence of damage or a seal defect in a membrane module; and the method is for a membrane module set including multiple membrane modules connected under gas detection piping communicating with primary spaces of the multiple membrane modules where raw water is supplied or secondary spaces in multiple membrane modules where treated water is extracted after the raw water is filtrated by membranes. The method includes a gas injection process where gas is injected into spaces opposite the primary or secondary spaces communicating with gas detection piping in the multiple membrane modules while the gas detection piping is filled with water, and a vibration detection process where a vibration sensor is brought into contact with a protrusion protruding outward from the gas detection piping to detect vibration of the gas detection piping.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: May 21, 2024
    Assignee: KUBOTA CORPORATION
    Inventors: Keishi Watanabe, Shintaro Nishimoto, Tetsuya Uenaka, Fang Zhao, Akira Matsunaga
  • Patent number: 11890581
    Abstract: A membrane defect inspection method is for a membrane module set including a plurality of membrane modules connected in parallel under a straight pipe portion of gas detection piping extending in a horizontal direction and communicating with primary spaces in the plurality of membrane modules to which raw water is supplied or secondary spaces. The method includes a gas injection process where gas is injected into spaces opposite to the primary spaces or the secondary spaces communicating with the gas detection piping while the gas detection piping is filled with water, and an echo detection process where an ultrasonic sensor is brought into contact with an end portion of the straight pipe portion of the gas detection piping, and a reflected wave of an ultrasonic wave transmitted from the ultrasonic sensor is detected.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: February 6, 2024
    Assignee: KUBOTA CORPORATION
    Inventors: Keishi Watanabe, Shintaro Nishimoto, Tetsuya Uenaka, Fang Zhao, Akira Matsunaga
  • Publication number: 20220111336
    Abstract: A membrane filtration device includes a plurality of membrane separation units vertically disposed in multiple stages. The membrane separation unit has a primary side communicating with a backwash drainage system and a flushing-air supply system to receive supplied raw water and a secondary side communicating with a backwash-water supply system to collect permeate. The backwash-water supply system includes a backwash-water main pipe and a plurality of backwash-water branch pipes to feed the backwash water into the membrane separation units. The backwash drainage system includes a plurality of backwash-drainage branch pipes and a backwash-drainage main pipe connected in parallel to the backwash-drainage branch pipes. The flushing-air supply system includes an air main pipe for passing flushing air upward and a plurality of air branch pipes for feeding flushing air into the membrane separation units, the air branch pipes being connected in parallel to the air main pipe.
    Type: Application
    Filed: December 12, 2019
    Publication date: April 14, 2022
    Applicant: KUBOTA CORPORATION
    Inventors: Shintaro NISHIMOTO, Keishi WATANABE, Tetsuya UENAKA, Fang ZHAO, Akira MATSUNAGA
  • Patent number: 11289571
    Abstract: The present invention provides a diode chip, including: a semiconductor chip, including a p-type first semiconductor layer and an n-type second semiconductor layer formed on the first semiconductor layer; a first pad separation trench, formed on the semiconductor chip in a manner of penetrating the second semiconductor layer till reaching the first semiconductor layer, and forming a first internal parasitic capacitance between the first semiconductor layer and the second semiconductor layer by separating a portion of the semiconductor chip from other regions; an inter-insulation layer, covering the second semiconductor layer; and a first electrode layer, being opposite to the region separated by the first pad separation trench with the inter-insulation layer interposed in between, and forming, between the first electrode layer and the semiconductor chip, a first external parasitic capacitance connected in series to the first internal parasitic capacitance.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: March 29, 2022
    Assignee: ROHM CO., LTD.
    Inventor: Keishi Watanabe
  • Publication number: 20220023802
    Abstract: A membrane defect inspection method that can detect damage in a filtrate membrane and can detect presence or absence of damage or a seal defect in a membrane module; and the method is for a membrane module set including multiple membrane modules connected under gas detection piping communicating with primary spaces of the multiple membrane modules where raw water is supplied or secondary spaces in multiple membrane modules where treated water is extracted after the raw water is filtrated by membranes. The method includes a gas injection process where gas is injected into spaces opposite the primary or secondary spaces communicating with gas detection piping in the multiple membrane modules while the gas detection piping is filled with water, and a vibration detection process where a vibration sensor is brought into contact with a protrusion protruding outward from the gas detection piping to detect vibration of the gas detection piping.
    Type: Application
    Filed: December 3, 2019
    Publication date: January 27, 2022
    Applicant: KUBOTA CORPORATION
    Inventors: Keishi WATANABE, Shintaro NISHIMOTO, Tetsuya UENAKA, Fang ZHAO, Akira MATSUNAGA
  • Publication number: 20210394123
    Abstract: A membrane defect inspection method is for a membrane module set including a plurality of membrane modules connected in parallel under a straight pipe portion of gas detection piping extending in a horizontal direction and communicating with primary spaces in the plurality of membrane modules to which raw water is supplied or secondary spaces. The method includes a gas injection process where gas is injected into spaces opposite to the primary spaces or the secondary spaces communicating with the gas detection piping while the gas detection piping is filled with water, and an echo detection process where an ultrasonic sensor is brought into contact with an end portion of the straight pipe portion of the gas detection piping, and a reflected wave of an ultrasonic wave transmitted from the ultrasonic sensor is detected.
    Type: Application
    Filed: December 3, 2019
    Publication date: December 23, 2021
    Applicant: KUBOTA CORPORATION
    Inventors: Keishi WATANABE, Shintaro NISHIMOTO, Tetsuya UENAKA, Fang ZHAO, Akira MATSUNAGA
  • Patent number: 11101071
    Abstract: The present disclosure provides a chip capacitor, including: a first capacitor unit formed over a substrate and including a first lower electrode, first dielectric layer and first upper electrode; a second insulating layer over the first capacitor unit; a second conductive layer over the second insulating layer, and includes a first wiring portion and a second wiring portion, the first wiring portion being connected to the first lower electrode by a first contact via and connected to a first pad by a third contact via, the second wiring portion being connected to the first upper electrode by a second contact via and connected to a second pad by a fourth contact via; a first external electrode connected to the first wiring portion; and a second external electrode connected to the second wiring portion.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: August 24, 2021
    Assignee: ROHM CO., LTD.
    Inventor: Keishi Watanabe
  • Publication number: 20210098449
    Abstract: The present disclosure provides a diode chip capable of attaining excellent electrical characteristics. The present disclosure provides a diode chip (1), including: a semiconductor chip (10) having a first main surface (11); a first pin junction portion (31) formed on a surface of the first main surface (11) with a first polarity direction; a first diode pair (37) (rectifier pair) including a first pn junction portion (35) separated from the first pin junction portion (31) and formed in the semiconductor chip (10) with the first polarity direction and a first reversed pin junction portion (38) connected to the first pn junction portion (35) in reversed direction and formed on the first main surface (11) with a second polarity direction; and a first junction separation trench (46) formed on the first main surface (11) in a manner of separating the first pin junction portion (31) and the first diode pair (37).
    Type: Application
    Filed: September 11, 2020
    Publication date: April 1, 2021
    Applicant: ROHM CO., LTD.
    Inventors: Keishi WATANABE, Junya YAMAGAMI
  • Publication number: 20210098572
    Abstract: The present invention provides a diode chip, including: a semiconductor chip, including a p-type first semiconductor layer and an n-type second semiconductor layer formed on the first semiconductor layer; a first pad separation trench, formed on the semiconductor chip in a manner of penetrating the second semiconductor layer till reaching the first semiconductor layer, and forming a first internal parasitic capacitance between the first semiconductor layer and the second semiconductor layer by separating a portion of the semiconductor chip from other regions; an inter-insulation layer, covering the second semiconductor layer; and a first electrode layer, being opposite to the region separated by the first pad separation trench with the inter-insulation layer interposed in between, and forming, between the first electrode layer and the semiconductor chip, a first external parasitic capacitance connected in series to the first internal parasitic capacitance.
    Type: Application
    Filed: July 7, 2020
    Publication date: April 1, 2021
    Applicant: ROHM CO., LTD.
    Inventor: Keishi WATANABE
  • Patent number: 10706993
    Abstract: A chip part is provided that includes a substrate in which an element region and an electrode region are set, an insulating film (a first insulating film and a second insulating film) which is formed on the substrate and which selectively includes an internal concave/convex structure in the electrode region on a surface, a first connection electrode and a second connection electrode which include, at a bottom portion, an anchor portion entering the concave portion of the internal concave/convex structure and which include an external concave/convex structure on a surface on the opposite side and a circuit element which is disposed in the element region and which is electrically connected to the first connection electrode and the second connection electrode.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: July 7, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Takuma Shimoichi, Yasuhiro Kondo, Keishi Watanabe, Takamichi Torii, Katsuya Matsuura
  • Patent number: 10681815
    Abstract: The composite chip component includes: plurality of chip elements which are disposed so as to be mutually spaced apart upon a common substrate, and which have mutually different functions; and a pair of electrodes which, in each of the chip elements, are formed on the surface of the substrate. As a result, it is possible to reduce the bond area (footprint) for the mounting substrate, and therefore, it is possible to provide a composite chip component capable of achieving efficiency of mounting operation.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: June 9, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Hiroshi Tamagawa, Koichi Niino, Eiji Nukaga, Keishi Watanabe
  • Publication number: 20200152380
    Abstract: The present disclosure provides a chip capacitor, including: a first capacitor unit formed over a substrate and including a first lower electrode, first dielectric layer and first upper electrode; a second insulating layer over the first capacitor unit; a second conductive layer over the second insulating layer, and includes a first wiring portion and a second wiring portion, the first wiring portion being connected to the first lower electrode by a first contact via and connected to a first pad by a third contact via, the second wiring portion being connected to the first upper electrode by a second contact via and connected to a second pad by a fourth contact via; a first external electrode connected to the first wiring portion; and a second external electrode connected to the second wiring portion.
    Type: Application
    Filed: November 7, 2019
    Publication date: May 14, 2020
    Applicant: ROHM CO., LTD.
    Inventor: Keishi Watanabe
  • Patent number: 10607779
    Abstract: A chip capacitor includes a substrate having a main surface, a first conductive film including a first connecting region and a first capacitor forming region and formed on the main surface of the substrate, a dielectric film covering the first capacitor forming region of the first conductive film, a second conductive film including a second connecting region facing to the first capacitor forming region of the first conductive film across the dielectric film, and a second capacitor forming region facing to the first capacitor forming region of the first conductive film across the dielectric film, a first external electrode electrically connected to the first connecting region of the first conductive film, and a second external electrode electrically connected to the second connecting region of the second conductive film.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: March 31, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Keishi Watanabe, Yasuhiro Kondo